Memory system integration: When multiple memory ICs are combined to provide the full addressable space, what technique identifies which specific IC is being accessed for a given address range?

Introduction / Context:
Large memory maps often require several chips in parallel (for width) or in banks (for depth). The CPU or memory controller must assert a unique chip-select to the correct device for each address window. This selection mechanism is fundamental digital design knowledge.

Given Data / Assumptions:

• Multiple memory ICs share data and address buses.
• Each device must respond only to its own address range.
• Objective: name the technique used for per-chip selection.

Concept / Approach:
Address decoding derives chip-select signals from upper address bits using logic gates or decoders (e.g., 2-to-4, 3-to-8). Decoding maps address subranges to one-hot chip-select lines, ensuring exactly one device is enabled at a time (except for deliberate mirroring or interleaving designs).

Step-by-Step Solution:

Verification / Alternative check:
Truth tables for decoders (e.g., 74HC138) and PLD/FPGA implementations illustrate straightforward mapping from address bits to chip selects.

Why Other Options Are Wrong:

• Memory refresh: Maintains DRAM data; not selection.
• Data encoding: Relates to data representation, not device selection.
• Memory paging: A software/OS technique; distinct from hardware address decoding.

Common Pitfalls:
Overlapping decode windows causing bus contention; forgetting to include write-protect or byte-enable logic where needed.

Final Answer:
address decoding