Difficulty: Easy
Correct Answer: a read cycle
Explanation:
Introduction / Context:
Memory transactions are named by their data direction and control strobes. When the system wants the contents of a location to appear on the data outputs, it performs a read. Correctly identifying read versus write is critical for designing timing and control logic.
Given Data / Assumptions:
Concept / Approach:
A read cycle retrieves data from a specified address. In SRAM, this typically requires CS active, WE inactive, and OE active. In DRAM, after RAS/CAS latch row and column with WE high, the selected cell's data appears at the outputs. By contrast, write cycles store data into the addressed location, and refresh cycles restore DRAM charge without presenting new external data for general use.
Step-by-Step Solution:
Verification / Alternative check:
Timing diagrams label tACC and tOE associated with read, whereas write timing references tDW/tWP for data setup and write pulse width.
Why Other Options Are Wrong:
Common Pitfalls:
Assuming that asserting CS alone produces data; OE/WE states also matter.
Final Answer:
a read cycle
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