DRAM control convention: In DRAM operations, it is assumed that the R/W (write enable) signal is in its ________ state during a ________ operation.

Introduction / Context:Control-signal polarity matters in DRAM timing. Many DRAM families use active-low write enables (sometimes labeled W or WE). Understanding which state corresponds to read or write avoids bus-contention bugs and corrupted data.

Given Data / Assumptions:

• Typical DRAM has RAS, CAS, and W/WE control pins.
• Write is requested when W is asserted (often LOW), while read occurs when W is deasserted (often HIGH).
• OE may qualify data outputs; internal details vary by family.

Concept / Approach:During a read, the device must not sample data-in; instead, it should drive data-out. Thus W remains in the deasserted (HIGH) state for read. During a write, W goes LOW to enable storing D at the addressed location while outputs are typically not driven.

Step-by-Step Solution:

Verification / Alternative check:Consult any classic DRAM timing: WE=HIGH indicates read; WE=LOW indicates write pulse width and data setup.

Why Other Options Are Wrong:

Common Pitfalls:Confusing output tri-state with control input levels or assuming all signals use active-high logic.

Final Answer:HIGH, read