Difficulty: Medium
Correct Answer: 16
Explanation:
Introduction / Context:
Designers often scale memory depth and width by combining smaller ICs. This exercise practices two key ideas: stacking for width (more bits per word) and banking for depth (more addresses).
Given Data / Assumptions:
Concept / Approach:
To reach the target depth, bank chips so that addresses select among 128k/16k = 8 banks. To reach the target width, place chips in parallel so that their data outputs concatenate. Each bank requires 2 devices in parallel to go from 4 bits to 8 bits. The total number of devices equals banks * devices per bank = 8 * 2 = 16.
Step-by-Step Solution:
Verification / Alternative check:
Check interface: All chips in a bank share addresses and chip enable; the paired devices in parallel provide D[7:4] and D[3:0].
Why Other Options Are Wrong:
Common Pitfalls:
Mixing up “k” (depth) scaling with width scaling, or forgetting that width expansion multiplies device count per bank.
Final Answer:
16
Discussion & Comments