Programmable Logic Device problems
- 1. How many combinations are handled in an LUT?
Options- A. 4
- B. 8
- C. 16
- D. 32 Also asked in: AIEEE, Bank Exams, CAT, Bank Clerk, Bank PO
Correct Answer: 16
- 2. CLB is the acronym for ________.
Options- A. Configurable Logic Block
- B. Configurable Logic Buffer
- C. Critical Logic Buffer
- D. Constant Logic Buffer Discuss
Correct Answer: Configurable Logic Block
- 3. What can the GAL22V10 do that the GAL16V8 cannot?
Options- A. It has an extra-large array.
- B. It is in-system programmable.
- C. It has twice the special function pins.
- D. All of the above Discuss
Correct Answer: It is in-system programmable.
- 4. What is the status of a tristate output buffer on a MAX7000S family device?
Options- A. It is permanently enabled or disabled.
- B. It is controlled by one of the two global output enable pins.
- C. It is controlled by other inputs or functions generated by other macrocells.
- D. All of the above Discuss
Correct Answer: All of the above
- 5. A slice consists of ________.
Options- A. only two logic cells
- B. between 2 and 8 logic cells
- C. up to 16 logic cells
- D. a single CLB Discuss
Correct Answer: only two logic cells
- 6. The GAL16V8 has:
Options- A. 16 dedicated inputs.
- B. 8 special function pins.
- C. 8 pins that are used as inputs or outputs.
- D. All of the above Discuss
Correct Answer: 8 pins that are used as inputs or outputs.
- 7. GAL is an acronym for ________.
Options- A. Generic Array Logic
- B. General Array Logic
- C. Giant Array Logic
- D. Generic Analysis Logic Discuss
Correct Answer: Generic Array Logic
- 8. The output of this circuit is always ________.
Options- A. 1
- B. 0
- C. A
- D. A Discuss
Correct Answer: A
- 9. A macrocell basically contains ________.
Options- A. a programmable AND-OR gate array and some input buffers
- B. an OR-gate array and some output logic
- C. an AND-OR gate array and some output logic
- D. licensed programming Discuss
Correct Answer: an OR-gate array and some output logic
- 10. Product terms are the outputs of which type of gate within a PLD array?
Options- A. OR
- B. XOR
- C. AND
- D. flip-flop Discuss
Correct Answer: AND
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