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Programmable Logic Device problems


  • 1. A look-up table is simply a truth table with all the possible output connections listed with their desired input response.

  • Options
  • A. True
  • B. False
  • Discuss
  • 2. Which of the following testing procedures has one or more external moving parts?

  • Options
  • A. Bed-of-nails
  • B. Flying probe
  • C. EXTEST
  • D. Boundary scan
  • Discuss
  • 3. PIA is an acronym for ________.

  • Options
  • A. Programmable Interface Array
  • B. Post Integrated Array
  • C. Programmable Input Array
  • D. Programmable Interconnect Array
  • Discuss
  • 4. The complex programmable logic device (CPLD) features a(n) ________ type of memory.

  • Options
  • A. volatile
  • B. nonvolatile
  • C. EPROM
  • D. volitile EPROM
  • Discuss
  • 5. An SPLD listed as 16H8 would have ________.

  • Options
  • A. active-HIGH outputs
  • B. active-LOW outputs
  • C. variable-level outputs
  • D. latches at the outputs
  • Discuss
  • 6. A(n) ________ is a section of embedded logic that is commonly found in FPGAs.

  • Options
  • A. LUT
  • B. core
  • C. DSP
  • D. PI
  • Discuss
  • 7. The final step in the device programming sequence is ________.

  • Options
  • A. compiling
  • B. downloading
  • C. simulation
  • D. synthesis
  • Discuss
  • 8. Field-programmable gate arrays (FGPAs) use ________ memory technology, which is ________.

  • Options
  • A. DRAM, nonvolatile
  • B. SRAM, nonvolatile
  • C. SRAM, volatile
  • D. RAM, volatile
  • Discuss
  • 9. Which one of the following is an embedded function of the Stratix II FPGA?

  • Options
  • A. AND-OR logic
  • B. Programmable SOP
  • C. Digital signal processing
  • D. None of the above
  • Discuss
  • 10. PALs tend to execute ________ logic.

  • Options
  • A. SAP
  • B. SOP
  • C. PLA
  • D. SPD
  • Discuss

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