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Flip-Flops problems


  • 1. Some flip-flops have invalid states.

  • Options
  • A. True
  • B. False
  • Discuss
  • 2. A positive edge-triggered flip-flop changes states with a HIGH-to-LOW transition on the clock input.

  • Options
  • A. True
  • B. False
  • Discuss
  • 3. ICs can perform sequential operations, including counting and data shifting.

  • Options
  • A. True
  • B. False
  • Discuss
  • 4. It takes four flip-flops to act as a divide-by-4 frequency divider.

  • Options
  • A. True
  • B. False
  • Discuss
  • 5. An astable multivibrator is sometimes referred to as a clock.

  • Options
  • A. True
  • B. False
  • Discuss
  • 6. The 7476 and 74LS76 are both dual flip-flops.

  • Options
  • A. True
  • B. False
  • Discuss
  • 7. An input which can only be accepted when an enable or trigger is present is called asynchronous.

  • Options
  • A. True
  • B. False
  • Discuss
  • 8. The key to edge-triggered sequential circuits in VHDL is the ________.

  • Options
  • A. ARCHITECTURE
  • B. PROCESS
  • C. FUNCTION
  • D. VARIABLE
  • Discuss
  • 9. Setup time specifies ________.

  • Options
  • A. the minimum time for the control levels to be maintained on the inputs prior to the triggering edge of the clock in order for data to be reliably clocked into the FF
  • B. the maximum time interval required for the control levels to remain on the inputs before the triggering edge of the clock in order for the data to be reliably clocked out of the FF
  • C. how long the operator has in order to get the flip-flop running before the maximum power level is exceeded
  • D. how long it takes the output to change states after the clock has transitioned
  • Discuss
  • 10. The inputs on a 7474 D flip-flop are S, R, D, and CLK ________ is/are synchronous.

  • Options
  • A. Only S
  • B. S and R
  • C. Only D
  • D. All of the above.
  • Discuss

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