Master-slave J-K flip-flops are called pulse-triggered or level-triggered device

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Question
Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.
Options
A. True
B. False

Correct Answer

False

Flip-Flops problems

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1. Which of the following describes the operation of a positive edge-triggered D flip-flop?
Options
A. If both inputs are HIGH, the output will toggle.
B. The output will follow the input on the leading edge of the clock.
C. When both inputs are LOW, an invalid state exists.
D. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.

3. The phenomenon of interpreting unwanted signals on J and K while C_p (clock pulse) is HIGH is called ________.
Options
A. parity error checking
B. ones catching
C. digital discrimination
D. digital filtering

4. Which of the following best describes the action of pulse-triggered FF's?
Options
A. The clock and the S-R inputs must be pulse shaped.
B. The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
C. A pulse on the clock transfers data from input to output.
D. The synchronous inputs must be pulsed.

5. With regard to a D latch, ________.
Options
A. the Q output follows the D input when EN is LOW
B. the Q output is opposite the D input when EN is LOW
C. the Q output follows the D input when EN is HIGH
D. the Q output is HIGH regardless of EN's input state

6. Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as shown below. Determine if the circuit is functioning properly, and if not, what might be wrong.
Options
A. The circuit is functioning properly.
B. Q2 is incorrect; the flip-flop is probably bad.
C. The input to flip-flop 3 (D2) is probably wrong; check the source of D2.
D. A bad connection probably exists between FF-3 and FF-4, causing FF-3 not to reset.

7. The symbols on this flip-flop device indicate ________.
Options
A. triggering takes place on the negative-going edge of the CLK pulse
B. triggering takes place on the positive-going edge of the CLK pulse
C. triggering can take place anytime during the HIGH level of the CLK waveform
D. triggering can take place anytime during the LOW level of the CLK waveform

10. As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:
Options
A. very long.
B. very short.
C. at a maximum value to enable the input control signals to stabilize.
D. of no consequence as long as the levels are within the determinate range of value.

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