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- Question
With regard to a D latch, ________.
Options- A. the Q output follows the D input when EN is LOW
- B. the Q output is opposite the D input when EN is LOW
- C. the Q output follows the D input when EN is HIGH
- D. the Q output is HIGH regardless of EN's input state
- Correct Answer
- the Q output follows the D input when EN is HIGH
- 1. What is the difference between the 7476 and the 74LS76?
Options- A. the 7476 is master-slave, the 74LS76 is master-slave
- B. the 7476 is edge-triggered, the 74LS76 is edge-triggered
- C. the 7476 is edge-triggered, the 74LS76 is master-slave
- D. the 7476 is master-slave, the 74LS76 is edge-triggered Discuss
- 2. Edge-triggered flip-flops must have:
Options- A. very fast response times.
- B. at least two inputs to handle rising and falling edges.
- C. a pulse transition detector.
- D. active-LOW inputs and complemented outputs. Discuss
- 3. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________.
Options- A. 1 kHz
- B. 2 kHz
- C. 4 kHz
- D. 16 kHz Discuss
- 4. A 555 operating as a monostable multivibrator has a C1 = 0.01 µF. Determine R1 for a pulse width of 2 ms.
Options- A. 200 kΩ
- B. 182 kΩ
- C. 91 kΩ
- D. 182 Ω Discuss
- 5. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.
Options- A. the clock pulse is LOW
- B. the clock pulse is HIGH
- C. the clock pulse transitions from LOW to HIGH
- D. the clock pulse transitions from HIGH to LOW Discuss
- 6. Which of the following best describes the action of pulse-triggered FF's?
Options- A. The clock and the S-R inputs must be pulse shaped.
- B. The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
- C. A pulse on the clock transfers data from input to output.
- D. The synchronous inputs must be pulsed. Discuss
- 7. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.
Options- A. parity error checking
- B. ones catching
- C. digital discrimination
- D. digital filtering Discuss
- 8. What is one disadvantage of an S-R flip-flop?
Options- A. It has no enable input.
- B. It has an invalid state.
- C. It has no clock input.
- D. It has only a single output. Discuss
- 9. Which of the following describes the operation of a positive edge-triggered D flip-flop?
Options- A. If both inputs are HIGH, the output will toggle.
- B. The output will follow the input on the leading edge of the clock.
- C. When both inputs are LOW, an invalid state exists.
- D. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock. Discuss
- 10. Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.
Options- A. True
- B. False Discuss
Flip-Flops problems
Search Results
Correct Answer: the 7476 is master-slave, the 74LS76 is edge-triggered
Correct Answer: a pulse transition detector.
Correct Answer: 2 kHz
Correct Answer: 182 kΩ
Correct Answer: the clock pulse transitions from LOW to HIGH
Correct Answer: The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
Correct Answer: ones catching
Correct Answer: It has an invalid state.
Correct Answer: The output will follow the input on the leading edge of the clock.
Correct Answer: False
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