Question 1

In computer architecture and digital systems, a bus is best described as a coordinated group of conductors used to carry digital signals between components—what is this group composed of?

Accepted Answer

Introduction / Context:A bus is a fundamental interconnection mechanism used in computer architecture, embedded systems, and digital electronics. Understanding what physically constitutes a bus clarifies how data, addresses, and control signals traverse between a CPU, memory, and peripherals.Given Data / Assumptions:A bus carries digital signals (0 or 1) representing data, addresses, and control lines.Physical realization in conventional boards and IC packages is via conductive traces or lines.We consider classical parallel buses (data/address/control) and do not limit to serial protocols.Concept / Approach:At the physical layer, digital signals require conductive paths. In printed circuit boards and inside chips, these paths are metallic conductors (often copper). Multiple such conductors grouped together and coordinated by timing constitute the bus. Higher-level terms like 'registers,' 'gates,' or 'transistors' refer to storage or active devices, not the passive medium carrying signals.Step-by-Step Solution:Identify what carries signals physically: conductive lines.A 'group' implies many parallel conductors forming data, address, and control lines.Therefore, a bus is a group of wires arranged and named by function (e.g., D[31:0], A[15:0], control).Active logic (gates, transistors) drive or sense those wires but are not the bus itself.Verification / Alternative check:Standard textbooks and microprocessor datasheets depict buses as bundles of lines (schematic thick lines) labeled with bit ranges, confirming that buses are made of wires/traces.Why Other Options Are Wrong:registers: storage elements; they source/sink data onto the bus but are not the bus.gates: logic primitives that process signals rather than passively carry them.transistors: semiconductor devices within gates and drivers; not the interconnect bundle.None of the above: incorrect because 'wires' is correct.Common Pitfalls:Confusing the medium (wires) with active circuitry; assuming 'bus' is purely logical with no physical meaning; overlooking that serial buses still map to one or more physical conductors.Final Answer:wires

Question 2

Within a CPU datapath, the Arithmetic Logic Unit (ALU) performs arithmetic and logical operations primarily on which numeral system representation, as opposed to human-readable decimal?

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Introduction / Context:The Arithmetic Logic Unit (ALU) is the core computation engine of processors and digital systems. While humans often express numbers in base 10 (decimal), digital hardware operates internally on a machine-native representation optimized for logic circuitry.Given Data / Assumptions:The ALU is implemented with logic gates (AND, OR, XOR, adders).Signals in hardware are binary (two discrete levels).Hexadecimal is a convenience for human representation of binary groups.Concept / Approach:Digital circuits encode information using bits (0/1). Adders, subtractors, shifters, and comparators are designed to manipulate bit vectors. Hex and decimal are higher-level notations; when they reach the ALU, they are already encoded as binary vectors. Therefore, the ALU processes binary numbers even if software shows hex or decimal to the user.Step-by-Step Solution:Recognize that wires in the datapath carry bit patterns.ALU blocks (e.g., ripple-carry adders) compute on those bit patterns directly.Thus, the operational numeral system at the hardware level is binary.Verification / Alternative check:Processor documentation specifies operand widths (e.g., 32-bit, 64-bit) and logic-level operations (bitwise ops), corroborating that computation occurs on binary words.Why Other Options Are Wrong:decimal: an external representation; internally, it becomes binary-coded forms.hexadecimal: a compact human-friendly grouping of binary; hardware still manipulates bits.All of the above: only one is fundamentally true for the ALU core.None of the above: incorrect because binary is correct.Common Pitfalls:Assuming that because programmers type decimal or hex, hardware computes in those bases; overlooking encoding layers like BCD that still reduce to binary logic operations.Final Answer:binary

Question 3

In positional numeral systems used for digital electronics, the hexadecimal digit set extends from 0–9 and A through which final letter?

Accepted Answer

Introduction / Context:Hexadecimal (base 16) is widely used to concisely express binary values, since each hex digit represents exactly 4 bits. Knowing the exact digit range is foundational for reading memory dumps and configuring low-level systems.Given Data / Assumptions:Hexadecimal base is 16.Decimal digits cover 0–9; additional symbols map to 10–15.Letters A–F represent 10–15 respectively.Concept / Approach:The hex sequence is {0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F}. Therefore, the final letter in the sequence is F. This mapping directly aligns with 4-bit binary: 0000 to 1111 equals 0 to F.Step-by-Step Solution:Count symbols: 10 numerals + 6 letters = 16 unique digits.Map letters to decimals: A=10, B=11, C=12, D=13, E=14, F=15.Therefore, the last hex letter is F.Verification / Alternative check:Any standard ASCII/Unicode table and programming language formatters (e.g., printf %X) confirm that hex digits end at F.Why Other Options Are Wrong:E: second-to-last; equals decimal 14.G: not a valid hex digit.D: equals decimal 13; not the final letter.None of the above: incorrect because F is correct.Common Pitfalls:Confusing base-16 with base-14 or assuming letters continue beyond F; misreading lowercase vs uppercase (both are accepted, but the set still ends at F).Final Answer:F

Question 4

In combinational logic design, what is the circuit called that selects data from two or more sources and forwards exactly one of them onto a single transmission line based on select inputs?

Accepted Answer

Introduction / Context:Routing signals efficiently is central to digital system design. When multiple sources must share a single destination channel, we use a selection mechanism governed by control lines to pick exactly one source at a time.Given Data / Assumptions:There are two or more candidate data sources.Only one source should appear on the output at a time.Selection is controlled by binary select lines.Concept / Approach:A multiplexer (MUX) is a combinational device that implements Y = D_k where k is chosen by the select inputs. It is the many-to-one counterpart of a demultiplexer (one-to-many). Encoders and decoders map between one-hot and binary codes rather than directly forwarding arbitrary data values.Step-by-Step Solution:Identify requirement: many inputs → one output.Map to device: this is the precise function of a multiplexer.Confirm control: select lines choose which input reaches the single line.Verification / Alternative check:Truth tables for 2:1, 4:1, or 8:1 multiplexers show output equals the selected input, validating the definition.Why Other Options Are Wrong:demultiplexer: performs one-to-many distribution, not many-to-one selection.encoder: converts one-hot inputs to binary code.decoder: expands binary code into one-hot outputs.None of the above: incorrect because multiplexer is correct.Common Pitfalls:Confusing MUX with DEMUX or thinking a decoder forwards arbitrary data rather than generating one-hot lines.Final Answer:multiplexer

Question 5

Simplify the Boolean expression (X + Y + XY)(X + Z) to its minimal sum form using absorption and distributive properties.

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Introduction / Context:Boolean simplification reduces logic cost, delay, and power. This problem reinforces core identities such as absorption and distributivity to reach a minimal or near-minimal expression suitable for implementation.Given Data / Assumptions:Expression: (X + Y + XY)(X + Z).Variables X, Y, Z are Boolean (0/1).Goal: simplify to a compact sum-of-terms form.Concept / Approach:Use absorption: A + AB = A. Therefore, Y + XY = Y. Then use the distributive identity: (X + A)(X + B) = X + AB. Apply these stepwise to collapse the expression.Step-by-Step Solution:Start: (X + Y + XY)(X + Z).Apply absorption on (Y + XY): X + (Y + XY) = X + Y.Now expression becomes: (X + Y)(X + Z).Use distributive form: (X + Y)(X + Z) = X + YZ.Result: X + YZ.Verification / Alternative check:Construct a quick truth check: when X=1, result is 1; when X=0, result reduces to YZ. This matches the product form behavior, confirming the simplification.Why Other Options Are Wrong:XZ + Y: does not match cases where X=0 and Y=1, Z=0 (gives 1 instead of YZ=0).X + Y + Z: over-approximates (too many 1s).XY + YZ: misses cases where X alone should drive 1.None of the above: incorrect because X + YZ is correct.Common Pitfalls:Forgetting absorption (Y + XY = Y), or expanding fully then miscombining minterms leading to longer forms.Final Answer:X + YZ

Question 6

Functionally comparing SR and JK flip-flops, which distinctive capability of the JK flip-flop resolves the SR invalid input and enables robust toggling behavior?

Accepted Answer

Introduction / Context:SR and JK flip-flops are foundational sequential elements. The SR latch/flip-flop has an invalid input condition when S=R=1. The JK flip-flop modifies the topology to eliminate this invalid state and provide a predictable toggle behavior when both inputs are asserted.Given Data / Assumptions:SR invalid state occurs at S=R=1.JK inputs are analogous to S and R, named J and K.Edge-triggered variants are typical in synchronous design.Concept / Approach:In a JK flip-flop, when J=K=1 at the active clock edge, the output toggles (Q(next) = NOT Q). This replaces the SR undefined condition with a well-defined transition, thanks to internal feedback and gating arrangements.Step-by-Step Solution:Identify SR limitation: S=R=1 → invalid/forbidden.Identify JK behavior: J=K=1 → toggle event on clock.Conclude the distinctive capability: accepting both inputs high safely and deterministically.Verification / Alternative check:JK truth tables show four modes: hold (00), reset (01), set (10), toggle (11). This confirms the resolution of the SR forbid state.Why Other Options Are Wrong:has a feed back path: true but not the key distinguishing functional capability asked.is faster: speed depends on implementation; not a defining functional difference.does not require external clock: false for synchronous JK flip-flops; latches differ.None of the above: incorrect because accepting both 1s is the core difference.Common Pitfalls:Confusing level-sensitive latches with edge-triggered flip-flops, and thinking feedback alone defines the difference rather than the resulting toggle mode.Final Answer:JK flip-flop accepts both inputs 1

Question 7

For a 6-input OR gate in combinational logic, identify the single input pattern that yields an output of 0 (logic low).

Accepted Answer

Introduction / Context:OR gates produce a logic 1 when any input is 1. The only time an OR gate outputs 0 is when every input is 0. This property generalizes regardless of the number of inputs (2, 4, 6, or more).Given Data / Assumptions:The gate is an ideal 6-input OR.Binary inputs are either 0 or 1.No wired-logic or inversion is present.Concept / Approach:The Boolean expression for an OR gate is Y = A + B + C + D + E + F. Y equals 0 only if A=B=C=D=E=F=0; any single 1 makes Y=1. This aligns with the inclusive definition of the OR operator.Step-by-Step Solution:Write the function: Y = A + B + C + D + E + F.Evaluate candidate words; if any bit is 1, Y becomes 1.Therefore, only 000000 produces Y=0.Verification / Alternative check:Truth tables for OR confirm a single 0-output row where all inputs are 0; all other rows output 1.Why Other Options Are Wrong:000111, 111000, 111111: each contains ones; the OR outputs 1.None of the above: incorrect because 000000 is correct.Common Pitfalls:Confusing OR with NOR or assuming exclusive OR semantics; mixing up active-high vs active-low conventions.Final Answer:000000

Question 8

In digital design methodology, the initial specification of input–output relationships for a logic function is typically captured using what foundational tabular artifact?

Accepted Answer

Introduction / Context:Before gates are drawn or HDL is written, designers clarify behavior by enumerating how outputs depend on inputs. This enumeration becomes the seed for simplification, implementation, and verification.Given Data / Assumptions:We are at the specification/derivation stage.Inputs are finite, allowing exhaustive listing.The goal is a deterministic combinational function mapping inputs to outputs.Concept / Approach:A truth table lists all input combinations and the corresponding outputs. From it, Karnaugh maps or Boolean algebra can be used to minimize logic and derive gate-level or HDL implementations.Step-by-Step Solution:Define inputs: e.g., A, B, C (n bits → 2^n rows).Enumerate all combinations and specify outputs Y.Use the table to extract minterms/maxterms and simplify.Verification / Alternative check:Cross-check with simulation: implementing the simplified logic must reproduce the truth table for all rows.Why Other Options Are Wrong:Standard/Two-stage/Two-dimensional: imprecise or descriptive terms, not the accepted artifact name.None of the above: incorrect because 'Truth' (truth table) is correct.Common Pitfalls:Skipping impossible input combinations; failing to specify don't-cares; mislabeling bit order leading to logic errors downstream.Final Answer:Truth

Question 9

Identify the TTL family class that (in its standard specification) can sink approximately 16 mA at logic low and source on the order of a fraction of a milliamp at logic high—what is this device class commonly called?

Accepted Answer

Introduction / Context:Transistor–Transistor Logic (TTL) families differ in speed, power, and I/O drive characteristics. Recognizing typical sink/source capabilities helps with fan-out calculations and interfacing to loads such as LEDs or other inputs.Given Data / Assumptions:Characteristic low-level sink current is roughly 16 mA for the reference family.High-level source capability is much smaller (around 0.4 mA or 400 microamps), reflecting TTL asymmetry.We refer to classic 74xx TTL specifications.Concept / Approach:Classic 'Standard TTL' (74xx) is known for strong sinking at logic 0 and weak sourcing at logic 1. Variants like LS (Low-power Schottky) and S (Schottky) alter speed/power, but the canonical numbers align most closely with Standard TTL expectations.Step-by-Step Solution:Match sink figure: ~16 mA low-level → hallmark of Standard TTL outputs.Match source figure: hundreds of microamps at high-level → also characteristic of Standard TTL.Therefore, the classification is 'Standard' TTL.Verification / Alternative check:Reference datasheets (e.g., 7400 series) show I_OL near 16 mA and I_OH in the sub-milliamp range, confirming the identification.Why Other Options Are Wrong:Schottky/Low-power/high-power: these modify speed/power trade-offs and typical currents; the given paired values best match Standard TTL.None of the above: incorrect because Standard is correct.Common Pitfalls:Misreading microamp (µA) as milliamp (mA); assuming symmetric source/sink drive; conflating CMOS output characteristics with TTL.Final Answer:Standard

Question 10

For an S–R latch implemented with cross-coupled NAND gates (active-low inputs), what condition results when both inputs R and S are driven low simultaneously?

Accepted Answer

Introduction / Context:S–R latches can be built from NOR or NAND gates. The NAND implementation uses active-low inputs, inverting the semantics compared to the NOR version. Understanding the forbidden/unstable input combination is critical for robust designs and avoiding metastability.Given Data / Assumptions:NAND S–R latch with cross-coupled feedback.Inputs labeled S (set) and R (reset) but active-low: a 0 asserts the function.We analyze simultaneous S=0 and R=0.Concept / Approach:For a NAND S–R latch, valid stable operations are: S=1,R=1 → hold; S=0,R=1 → set; S=1,R=0 → reset. When S=0 and R=0, both NAND outputs are forced high initially; upon release, the state can race unpredictably depending on internal delays, rendering the condition invalid (race/forbidden).Step-by-Step Solution:Apply inputs S=0, R=0 to NANDs → each NAND sees at least one 0 at an input.Both outputs momentarily go to 1, breaking the complementary guarantee.When inputs are released, slight skews can lead to either final state, hence 'race'/undefined.Verification / Alternative check:Truth tables and timing diagrams in digital design texts mark S=R=0 (for NAND latch) as forbidden/invalid, paralleling S=R=1 for the NOR latch.Why Other Options Are Wrong:set/reset: those occur with one low, one high, not both low.no change: incorrect because both outputs are forced high; the previous state is not preserved deterministically.None of the above: incorrect because 'race' describes the invalid condition.Common Pitfalls:Swapping NOR and NAND conventions; assuming active-high behavior applies unchanged; overlooking that asynchronous release timing leads to unpredictability.Final Answer:race

Question 11

In digital electronics, an OR gate can be conceptualized using simple switch analogies—how should the switches be connected to reflect the OR function (so the output path conducts if any input is asserted)?

Accepted Answer

Introduction / Context:Digital logic gates are often explained with intuitive switch analogies. An OR gate outputs logic high when any input is high. Mapping this behavior to basic on/off switches helps students visualize conduction paths and understand why OR differs from AND at a physical or conceptual level.Given Data / Assumptions:Positive logic is assumed: closed switch = logic 1 path enabled.Goal: replicate OR behavior using idealized switches.Output is considered connected to a source through a network of input-controlled switches.Concept / Approach:If the output must conduct when any input is asserted, then each input should provide an independent conducting path. The natural way to realize independent paths is to place the input-controlled elements in parallel. In parallel, closure of any one branch establishes continuity from source to output, mirroring the inclusive OR truth table.Step-by-Step Solution:1) Define the target behavior: output conducts if A = 1 OR B = 1 (or any input = 1).2) Series vs parallel: series requires all switches to close for current to flow (AND behavior); parallel requires at least one branch closed for current to flow (OR behavior).3) Construct the network: connect one switch per input in parallel between source and output.4) Verify: if any one input closes, the output node is driven, satisfying OR.Verification / Alternative check:Truth-table comparison shows that parallel branches reproduce the OR column exactly: only when all branches are open (all inputs low) does the output fail to conduct.Why Other Options Are Wrong:Series switches implement AND (all must close). 'MOS transistors connected in series' describes an AND-like pull-down in CMOS, not the OR analogy asked. 'All of the above' cannot be correct because series contradicts the OR requirement.Common Pitfalls:Confusing CMOS pull-up/pull-down topology (mixed series/parallel) with the simple switch analogy, and forgetting that OR requires alternative, not cumulative, paths.Final Answer:switches connected in parallel

Question 12

In signal-level conventions, a positive-logic AND gate is equivalent to which negative-logic gate (i.e., when 0 and 1 meanings are swapped for inputs and output)?

Accepted Answer

Introduction / Context:Logic functions depend not only on gate symbols but also on the interpretation of voltage levels. Under positive logic, high = 1 and low = 0. Under negative logic, this interpretation is inverted. Understanding equivalence between positive- and negative-logic gates is a classic application of De Morgan’s transformations and level conventions.Given Data / Assumptions:Positive logic: high means 1, low means 0.Negative logic: high means 0, low means 1 (polarity inverted).We seek the negative-logic gate that performs the same Boolean relation as a positive-logic AND.Concept / Approach:When signal interpretation flips, the logical operations dualize. A positive-logic AND corresponds to a negative-logic OR: both represent the same underlying hardware relation viewed through opposite level meanings. Intuitively, if asserting any negative-logic input (i.e., pulling it low in physical voltage) suffices to assert the output (also low), then in negative-logic terms the function is OR while in positive-logic terms the same hardware is AND.Step-by-Step Solution:1) Start with positive-logic AND: F = A * B with 1 as high.2) Re-interpret with negative logic (invert meanings): low becomes logical 1, high becomes logical 0.3) Under the inverted interpretation, the same physical truth table maps to OR between negative-logic variables.4) Hence the equivalence: positive AND ≡ negative OR.Verification / Alternative check:Apply De Morgan’s view of complemented variables and observe that complementing inputs and output of OR yields AND and vice versa when switching logic sense.Why Other Options Are Wrong:NAND/NOR involve output inversion relative to AND/OR, which is not what a pure logic-sense swap implies. 'AND gate' does not change with a polarity swap. Thus 'OR gate' is the correct negative-logic equivalent.Common Pitfalls:Confusing negative logic (level interpretation) with inserting physical inverters, and mixing up NAND/NOR identities with logic-sense equivalence.Final Answer:OR gate

Question 13

For a logic gate abstraction, how many input signals can a gate legally accept in digital design practice?

Accepted Answer

Introduction / Context:Logic gates are defined by a Boolean function mapping N inputs to a single output. While textbooks often show 2-input gates for simplicity, practical gates can be unary (one input) or have many inputs (3, 4, 8, or more). Understanding this flexibility avoids artificial constraints during circuit design or exam questions.Given Data / Assumptions:Gate = combinational device with fixed truth table.Technology could be TTL, CMOS, ECL, etc.No specific fan-in limit is imposed by the question.Concept / Approach:Unary gates (NOT/inverter, buffer) accept one input. Multi-input gates (AND, OR, NAND, NOR) accept 2 or more inputs; many families offer 3-input, 4-input, or 8-input variants. Therefore the correct general statement is that a gate may have one input or more than one input. The option claiming “two only” is false; two is common but not exclusive.Step-by-Step Solution:1) Identify unary example: NOT gate (1 input).2) Identify multi-input examples: 3-input NAND, 4-input OR, etc.3) Conclude that valid fan-in includes 1 and greater than 1.4) Select the option that includes both cases.Verification / Alternative check:Standard logic catalogs list NAND/NOR/AND/OR in multiple input counts; data sheets confirm functional equivalence across different fan-in sizes.Why Other Options Are Wrong:'two only' is overly restrictive. 'one' or 'more than one' alone are incomplete. 'None of the above' fails because a correct inclusive statement exists.Common Pitfalls:Assuming all logic gates are 2-input due to common diagrams, and ignoring fan-in limits that are technology-specific rather than theoretical.Final Answer:both (a) and (b)

Question 14

Convert the decimal number 67₁₀ to its octal representation (showing the correctly base-tagged form).

Accepted Answer

Introduction / Context:Base conversion is a staple skill in digital systems. Octal is convenient because each octal digit corresponds to three binary bits, providing a compact representation of binary values (especially in early microprocessor documentation and permissions in operating systems). Here we convert a base-10 integer to base 8.Given Data / Assumptions:Decimal input n = 67.Target base = 8 (octal).Output expressed with an explicit base tag 8.Concept / Approach:Use repeated division by the target base and collect remainders. For octal, divide by 8; the remainders (0–7) form digits from least to most significant when read in reverse order of computation. This algorithm mirrors positional weighting in base systems.Step-by-Step Solution:1) 67 / 8 = 8 remainder 3 → least significant octal digit = 3.2) 8 / 8 = 1 remainder 0 → next digit = 0.3) 1 / 8 = 0 remainder 1 → most significant digit = 1.4) Reading remainders backward gives 103, hence 1038.Verification / Alternative check:Decimal check: 18^2 + 08^1 + 3*8^0 = 64 + 0 + 3 = 67, confirming correctness.Why Other Options Are Wrong:1008 represents 64, not 67. 1098 exceeds digit range (digit 9 is invalid in octal). 998 is invalid (9 not allowed). 'None of the above' is wrong because 1038 is correct.Common Pitfalls:Forgetting to reverse the remainder order, or mistakenly using base 2/16 groupings instead of base 8 division.Final Answer:1038

Question 15

In pulse and switching waveforms, what is the name for the time it takes a pulse to fall from 90% to 10% of its maximum amplitude?

Accepted Answer

Introduction / Context:Timing parameters characterize how quickly digital or analog signals transition between levels. Standardized definitions use percentage points to avoid noise near the extremes. Recognizing the correct term for the downward transition is essential in waveform specs and data sheets.Given Data / Assumptions:We consider a pulse falling from a high level to a low level.Measurement points are 90% and 10% of the maximum amplitude.Standard positive logic conventions apply.Concept / Approach:The time from 10% to 90% during a rising edge is the rise time. The time from 90% to 10% during a falling edge is the fall time, also called the decay time in many texts. Propagation delay refers to the time between input stimulus and output response (e.g., tPLH, tPHL), not the edge slewing interval itself. Therefore, the given description matches decay (fall) time.Step-by-Step Solution:1) Identify transition direction: high to low (falling edge).2) Note measurement window: 90% down to 10% of Vmax.3) Standard term: fall time (aka decay time).4) Conclude the correct option is 'decay time' per provided choices.Verification / Alternative check:Oscilloscope measurements and component datasheets define tr (rise) = 10%→90% and tf (fall/decay) = 90%→10%, aligning with the chosen term.Why Other Options Are Wrong:'rise time' is for low→high transitions. 'binary level transition period' is vague and nonstandard. 'propagation delay' measures input-to-output latency, not edge slope.Common Pitfalls:Confusing propagation delay with slew times, or using 0–100% windows which are sensitive to noise and saturation effects.Final Answer:decay time

Question 16

Among common flip-flop designs, which configuration is inherently free from the race-around problem under edge-triggered operation?

Accepted Answer

Introduction / Context:The race-around problem occurs in level-triggered JK configurations when both inputs are high and the clock level remains enabled, causing the output to toggle rapidly within the same clock interval. A classic solution is master–slave staging or edge-triggering, which blocks multiple toggles during a single clock event.Given Data / Assumptions:We consider standard synchronous flip-flop types.Clocking philosophy: level vs edge triggering.Goal: identify a design that avoids race-around without additional constraints on pulse width.Concept / Approach:The master–slave JK flip-flop uses two latches in series: the master captures input on one clock level, and the slave updates output on the opposite level. This staging ensures that, even if J = K = 1, only a single toggle occurs per clock pulse because the slave does not see the master updating continuously during the same phase.Step-by-Step Solution:1) Identify the condition for race-around: J = K = 1 with a long level-enabled clock.2) Note that single-latch level devices (plain JK/T) can toggle repeatedly during the active level.3) Master–slave arrangement separates sampling and updating phases.4) Therefore, only one effective toggle occurs, eliminating race-around.Verification / Alternative check:Edge-triggered JK or T implementations also avoid race-around by design; master–slave is the canonical level-based method to enforce single action per clock.Why Other Options Are Wrong:Plain T and SR implementations can exhibit hazards or race behavior depending on clock width and input conditions. Hence they are not inherently free of race-around.Common Pitfalls:Assuming any JK flip-flop is safe without considering clocking style, or forgetting that master–slave specifically addresses the level-triggered hazard.Final Answer:master slave JK flip-flop

Question 17

Applying De Morgan’s law, what overall logic function results from inverting each input of an AND gate (inputs only, output not inverted)?

Accepted Answer

Introduction / Context:Transforming logic by adding input inverters is a fundamental technique in gate-level design. De Morgan’s laws provide the algebraic toolset to predict the resulting function without exhaustive truth tables. Here we start with an AND gate and invert each input before it reaches the gate, while leaving the output unchanged.Given Data / Assumptions:Base gate: AND with inputs A, B, ...Each input is inverted prior to the AND stage.No inversion on the output node.Concept / Approach:Let A' = NOT A and B' = NOT B. The gate computes F = A' AND B'. By De Morgan’s law, (NOT A) AND (NOT B) = NOT (A OR B). This definition is precisely the NOR function of the original (non-inverted) variables. Thus, input inversion around an AND gate implements NOR overall.Step-by-Step Solution:1) Substitute inverted inputs: F = (NOT A) AND (NOT B).2) Apply De Morgan: F = NOT (A OR B).3) Recognize the canonical gate: NOR(A, B).4) Generalize: with n inputs, inverting all inputs to AND yields n-input NOR.Verification / Alternative check:Truth-table enumeration for two inputs confirms that F = 1 only when A = 0 and B = 0, matching NOR.Why Other Options Are Wrong:OR requires output inversion as well. NAND results from inverting only the output of AND. XOR is unrelated to De Morgan’s complement-of-sum relation.Common Pitfalls:Forgetting whether the output is inverted, and mixing up the two De Morgan identities (complement of product vs complement of sum).Final Answer:NOR

Question 18

For a multi-input NOR gate, what must the input conditions be to obtain a logic-high output at the gate's output?

Accepted Answer

Introduction / Context:The NOR gate is the negation of the OR function. Understanding its truth table is vital because NOR (like NAND) is functionally complete—any Boolean function can be built from it. Here we recall the specific input condition that produces an asserted (high) output from a NOR gate.Given Data / Assumptions:Positive logic convention: high = 1, low = 0.NOR = NOT(OR of inputs).The device may have two or more inputs.Concept / Approach:OR outputs high if any input is high. NOR inverts that outcome, thus it outputs high only in the single case where the OR would be low—namely when all inputs are low. Therefore, every input must be low to obtain a high output from NOR.Step-by-Step Solution:1) OR rule: if any input = 1 → OR output = 1.2) NOR = NOT(OR), so if OR output = 1 → NOR output = 0.3) The only time OR = 0 is when all inputs = 0.4) Hence NOR output = 1 only when all inputs are low.Verification / Alternative check:Truth tables for 2-, 3-, and 4-input NOR devices consistently show a single high-output row corresponding to all-zero inputs.Why Other Options Are Wrong:'high' or 'some low some high' would cause the OR to be 1, making NOR = 0. '1's' is just another way to say high inputs, which likewise drive NOR low.Common Pitfalls:Mixing up NOR with NAND (which outputs low only if all inputs are high) and forgetting that NOR’s asserted output corresponds to the all-zero input combination.Final Answer:low

Question 19

Compute the 2's complement of the 16-bit binary word 0011 0101 1001 1100 and report the result as grouped bits.

Accepted Answer

Introduction / Context:Two’s complement is the dominant representation for signed integers in computer systems. It enables straightforward addition/subtraction using the same binary adder hardware. Converting a positive binary word to its two’s complement negative (or vice versa) uses a simple invert-plus-one recipe.Given Data / Assumptions:Original 16-bit word: 0011 0101 1001 1100.Spaces are visual groupings; they do not affect bit values.We apply the standard 2’s complement operation.Concept / Approach:The two’s complement of a binary word W is computed by inverting every bit (forming the one’s complement) and then adding 1 to the result. This effectively computes 2^n − W for an n-bit word, which represents the arithmetic negation modulo 2^n.Step-by-Step Solution:1) Start: W = 0011 0101 1001 1100.2) One’s complement (invert each bit): 1100 1010 0110 0011.3) Add 1: 1100 1010 0110 0011 + 0000 0000 0000 0001 = 1100 1010 0110 0100.4) Result: 1100 1010 0110 0100.Verification / Alternative check:Hex cross-check: 0011 0101 1001 1100 = 0x359C; two’s complement = 0xCA64. Adding 0x359C + 0xCA64 = 0x10000 (overflow ignored in 16 bits), confirming correctness.Why Other Options Are Wrong:Options a, b, and d differ by one or more bits; none equals the computed sum after the +1 step. Therefore option c is the unique correct result.Common Pitfalls:Forgetting the +1 after inversion, mishandling carries across grouped spaces, or inverting only up to the first 1 from the right (which is an alternative shortcut but easy to misapply).Final Answer:1100 1010 0110 0100

Question 20

Convert the octal number 112₈ to hexadecimal, expressing the final answer with a base-16 tag.

Accepted Answer

Introduction / Context:Conversions among octal, decimal, and hexadecimal are routine in low-level programming and digital hardware work. Because octal groups bits in threes and hexadecimal groups bits in fours, it is often simplest to pass through decimal or binary as an intermediate step for clarity and to avoid mistakes.Given Data / Assumptions:Input: 1128 (base 8).Target: base 16 (hexadecimal).Standard positional weights apply.Concept / Approach:Method 1 (decimal intermediate): compute decimal value using 8^n weights, then convert decimal to hex. Method 2 (binary intermediate): map each octal digit to a 3-bit binary triplet, then regroup into 4-bit nibbles for hex mapping. Either yields the same result.Step-by-Step Solution:1) Decimal method: 1128 = 18^2 + 18^1 + 28^0 = 64 + 8 + 2 = 74₁₀.2) Convert 74₁₀ to hex: 74 / 16 = 4 remainder 10 → 4A16.3) Binary method (check): 1→001, 1→001, 2→010 → 001 001 010 = 0010 0101 0₂ = 0100 1010₂ (pad left) = 0x4A.4) Both methods agree: 4A16.Verification / Alternative check:Reconvert back: 0x4A = 416 + 10 = 64 + 10 = 74 = 1128, confirming correctness.Why Other Options Are Wrong:5A16 equals 90 decimal; 1516 equals 21 decimal; 2016 equals 32 decimal. None match 74 decimal.Common Pitfalls:Mismapping octal digits to 4-bit nibbles directly without regrouping, or forgetting to pad the most significant group when converting via binary.Final Answer:4A16

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