For an S–R latch implemented with cross-coupled NAND gates (active-low inputs), what condition results when both inputs R and S are driven low simultaneously?

Introduction / Context:S–R latches can be built from NOR or NAND gates. The NAND implementation uses active-low inputs, inverting the semantics compared to the NOR version. Understanding the forbidden/unstable input combination is critical for robust designs and avoiding metastability.

Given Data / Assumptions:

• NAND S–R latch with cross-coupled feedback.
• Inputs labeled S (set) and R (reset) but active-low: a 0 asserts the function.
• We analyze simultaneous S=0 and R=0.

Concept / Approach:For a NAND S–R latch, valid stable operations are: S=1,R=1 → hold; S=0,R=1 → set; S=1,R=0 → reset. When S=0 and R=0, both NAND outputs are forced high initially; upon release, the state can race unpredictably depending on internal delays, rendering the condition invalid (race/forbidden).

Step-by-Step Solution:

Verification / Alternative check:Truth tables and timing diagrams in digital design texts mark S=R=0 (for NAND latch) as forbidden/invalid, paralleling S=R=1 for the NOR latch.

Why Other Options Are Wrong:

• set/reset: those occur with one low, one high, not both low.
• no change: incorrect because both outputs are forced high; the previous state is not preserved deterministically.
• None of the above: incorrect because 'race' describes the invalid condition.

Common Pitfalls:Swapping NOR and NAND conventions; assuming active-high behavior applies unchanged; overlooking that asynchronous release timing leads to unpredictability.

Final Answer:race