Functionally comparing SR and JK flip-flops, which distinctive capability of the JK flip-flop resolves the SR invalid input and enables robust toggling behavior?

Introduction / Context:
SR and JK flip-flops are foundational sequential elements. The SR latch/flip-flop has an invalid input condition when S=R=1. The JK flip-flop modifies the topology to eliminate this invalid state and provide a predictable toggle behavior when both inputs are asserted.

Given Data / Assumptions:

• SR invalid state occurs at S=R=1.
• JK inputs are analogous to S and R, named J and K.
• Edge-triggered variants are typical in synchronous design.

Concept / Approach:
In a JK flip-flop, when J=K=1 at the active clock edge, the output toggles (Q(next) = NOT Q). This replaces the SR undefined condition with a well-defined transition, thanks to internal feedback and gating arrangements.

Step-by-Step Solution:

Verification / Alternative check:
JK truth tables show four modes: hold (00), reset (01), set (10), toggle (11). This confirms the resolution of the SR forbid state.

Why Other Options Are Wrong:

• has a feed back path: true but not the key distinguishing functional capability asked.
• is faster: speed depends on implementation; not a defining functional difference.
• does not require external clock: false for synchronous JK flip-flops; latches differ.
• None of the above: incorrect because accepting both 1s is the core difference.

Common Pitfalls:
Confusing level-sensitive latches with edge-triggered flip-flops, and thinking feedback alone defines the difference rather than the resulting toggle mode.

Final Answer:
JK flip-flop accepts both inputs 1