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Memory timing — The operation that stores data at the addressed location after presenting a new valid address is called what?

Difficulty: Easy

Correct Answer: a write cycle

Explanation:


Introduction / Context:
Digital systems interact with memory using well-defined bus timing. After a valid address is placed on the bus, the controller either reads the contents at that location or stores new data there. Correctly naming these operations is fundamental to interpreting datasheets and designing memory controllers.

Given Data / Assumptions:

  • “New address” means the address bus has been updated and stabilized.
  • Separate control signals indicate read or write intent (e.g., /RD, /WR).
  • We are discussing generic semiconductor memories (RAM, ROM, etc.).


Concept / Approach:
A write cycle is the sequence in which the controller asserts the write control, drives the data bus with the value to be stored, and meets setup/hold and pulse-width timing so the memory latches the new data into the addressed cell. In contrast, a read cycle retrieves data from the selected address, and a refresh cycle is specific to DRAM retention rather than user data storage. Chip select simply enables a device; it is not an operation by itself.

Step-by-Step Solution:

Apply address A on the bus and assert chip select to enable the target memory.Drive the data bus with the value D intended for storage.Assert write control for the required write pulse width; meet setup/hold times so the memory stores D at A.


Verification / Alternative check:

Check timing diagrams in RAM datasheets: “Write cycle timing” explicitly shows address setup, data valid window, and /WE pulse controlling storage.


Why Other Options Are Wrong:

a read cycle: Fetches data; does not store it.a refresh cycle: Maintains DRAM charge but does not accept external user data.chip select: An enabling signal, not a complete operation storing data.


Common Pitfalls:

Confusing enabling a device (chip select) with performing a write.Thinking “refresh” is a type of write; it is internal maintenance for DRAM integrity.


Final Answer:

a write cycle
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