Difficulty: Easy
Correct Answer: every 2 milliseconds
Explanation:
Introduction / Context:
DRAM cells store charge on tiny capacitors that leak over time. To preserve data, each row must be periodically refreshed by re-reading and re-writing it within a device-specified refresh interval. Classical 16K × 1 devices like the 2118 provide a representative requirement.
Given Data / Assumptions:
Concept / Approach:
Historical DRAMs often require that all rows be refreshed within approximately 2 ms (some families use 4 ms or similar, but the 2 ms figure is typical for this class). Controllers satisfy this by distributing refresh cycles across time, ensuring that each row is accessed before its charge decays below a safe threshold.
Step-by-Step Solution:
Verification / Alternative check:
Datasheets specify maximum refresh interval per row set; meeting or beating that interval guarantees retention across the array.
Why Other Options Are Wrong:
Common Pitfalls:
Assuming refresh is optional; if missed, data corruption is inevitable in DRAM.
Final Answer:
every 2 milliseconds
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