Row/column pin sharing in DRAM — the technique that reuses the same external pins to carry first the row address and then the column address is called _____.

Introduction / Context:
To keep packages small and costs low, DRAM devices reduce the number of address pins by time-multiplexing the address bus. Instead of dedicating separate pins to all row and column bits, the same pins are driven twice—first with the row portion, then with the column portion—latched by distinct strobes.

Given Data / Assumptions:

• The question asks for the name of this pin-sharing technique.
• We assume conventional DRAM signaling with RAS (Row Address Strobe) and CAS (Column Address Strobe).
• Focus is on external pin reuse, not internal banking or refresh.

Concept / Approach:
“Address multiplexing” is the correct term. During a DRAM access, the controller presents the row address and asserts RAS to latch it, then presents the column address and asserts CAS. This allows, for example, a device with 12 row + 10 column bits (22 total) to expose only 12 pins externally and reuse them, dramatically easing pin count and package size.

Step-by-Step Solution:

Verification / Alternative check:
Any DRAM timing diagram shows separate RAS and CAS phases with the same address pins carrying different portions, confirming the multiplexing behavior.

Why Other Options Are Wrong:

Common Pitfalls:
Confusing the control signals (RAS/CAS) with the overall technique; assuming multiplexing applies to data pins—here it specifically refers to address pins.

Final Answer:
Address multiplexing