Semiconductor memory timing definition: What is the term for the time interval between a memory device receiving a valid new address on its inputs and the corresponding data becoming available at the data outputs (valid to read)?

Introduction / Context:
When working with semiconductor memories (SRAM, DRAM, ROM, and their derivatives), timing parameters define how quickly a processor or controller can obtain valid data. One of the most fundamental parameters is the interval from presenting an address to the memory until the output data is valid and stable. This concept is crucial for bus timing, wait-state insertion, and overall system performance.

Given Data / Assumptions:

• A new address is applied to a memory chip’s address pins.
• Appropriate control signals (chip enable, output enable) are asserted.
• We are interested in the time until data outputs provide correct, stable data.

Concept / Approach:
The standard timing term for address-to-data latency is access time. It specifies how long after a valid address (and enables) the memory guarantees valid data at its outputs. Designers compare access time with the processor’s cycle time to determine whether wait states are needed. Do not confuse this with bus speed (a system-level metric) or generic read/write “speed,” which are not formal timing parameters in datasheets.

Step-by-Step Solution:

Verification / Alternative check:
Open any SRAM/DRAM/ROM datasheet: the principal read timing is listed as t_ACC or similar, defined from address (and control) valid to data valid. This aligns exactly with the scenario in the stem.

Why Other Options Are Wrong:
Bus speed: a system-wide interface rate, not a device timing. Read/write speed: informal and ambiguous. Write/data speed: not a standard timing term. Address setup time: the minimum time address must be stable before a strobe, not the address-to-data latency.

Common Pitfalls:
Confusing t_ACC with t_OE (output enable to data valid) or with synchronous timing (clock-to-Q in SDRAM/DDR). Always read the specific timing diagrams.

Final Answer:
Access time