Pin-count reduction technique in memory ICs: To keep the package pin count manageable while addressing large arrays, manufacturers commonly use which technique on address lines?

Introduction / Context:
Large memory arrays require many address lines. To avoid packages with impractically high pin counts, memory manufacturers employ techniques to present addresses in phases, drastically reducing the number of physical pins while still reaching every cell. Understanding this method is essential for interfacing DRAM and SDRAM parts that separate row and column addressing.

Given Data / Assumptions:

• Goal: fewer package pins while still accessing a large address space.
• Typical memories: DRAM families separate row and column addressing.
• Controllers provide strobes that qualify each phase of the address.

Concept / Approach:
Address multiplexing sends part of the address (row) during one phase and the remaining part (column) during another, using the same physical pins. Row Address Strobe (RAS) and Column Address Strobe (CAS) latch each portion internally. This halves the number of address pins compared with providing the entire address in parallel, enabling compact packages and lower costs.

Step-by-Step Solution:

Verification / Alternative check:
DRAM datasheets show A0–An pins used for both row and column, with RAS/CAS strobes. SRAMs without multiplexing typically require more pins or smaller densities.

Why Other Options Are Wrong:
MOSFET architecture is generic device physics. Address decoding is internal selection logic, not a pin-saving method. Demultiplexing is the inverse operation at the receiver. On-chip PLLs relate to clocks, not address pin reduction.

Common Pitfalls:
Confusing address multiplexing with time-multiplexed data; note that some buses multiplex address and data as well, but the question is specifically about address lines within memory ICs.

Final Answer:
Address multiplexing