DRAM refresh interval (typical legacy specification): Refreshing a dynamic RAM (DRAM) cell array typically must occur about every ____ to prevent charge loss from the storage capacitors.

Introduction / Context:
Unlike SRAM, DRAM stores each bit as charge on a tiny capacitor, which leaks over time and must be periodically refreshed. The refresh interval is a key parameter: controllers must cycle through all rows before the charge decays below a reliable threshold. While modern DRAM families specify different intervals (for example, on the order of tens of milliseconds), many foundational texts and legacy exam questions cite a much shorter, illustrative interval for simplicity.

Given Data / Assumptions:

• Classic/legacy DRAM context used in many electronics quizzes.
• We seek a typical refresher interval value from those provided.
• Goal is to prevent data loss due to charge leakage.

Concept / Approach:
DRAM cells lose charge exponentially. A refresh controller (internal or external) ensures each row is refreshed within the specified maximum interval. Many academic sources historically use ≈2 ms as a teaching value for “must refresh periodically,” even though specific commercial parts may list values such as 4 ms, 8 ms, or 64 ms total across all rows. From the given choices, 2 ms fits the classic requirement often quoted in fundamentals questions.

Step-by-Step Solution:

Verification / Alternative check:
Examine traditional exam prep materials: many specify 2 ms, while modern JEDEC parts may state 64 ms (or temperature-dependent values). The question’s option set and phrasing indicate the simpler legacy figure is expected.

Why Other Options Are Wrong:
2 µs and 8 µs are far too short for typical DRAM; 8 ms or larger can be correct for some devices but are not the historical “textbook” value used in basic quizzes like this one.

Common Pitfalls:
Assuming a single universal number; in practice, always consult the specific DRAM’s datasheet and temperature derating tables.

Final Answer:
2 ms