Timing of XOR output for overlapping pulses Two positive pulses are applied to a 2-input XOR gate. Pulse X1 has width 75 µs starting at t = 0 µs. Pulse X2 has width 15 µs starting at t = 20 µs (thus ending at t = 35 µs). Describe the XOR output timing in terms of pulse widths and separations.

Introduction / Context:
The exclusive-OR (XOR) gate outputs logic 1 when its inputs are different and logic 0 when they are the same. When pulses overlap in time, the XOR output toggles according to intervals of mismatch vs. match. Timing analysis of overlaps is a core skill for digital timing diagrams.

Given Data / Assumptions:

• Input X1: HIGH from t = 0 µs to t = 75 µs (tw = 75 µs).
• Input X2: HIGH from t = 20 µs to t = 35 µs (tw = 15 µs), starting 20 µs after X1 rises.
• XOR rule: output = 1 when exactly one input is HIGH; otherwise 0.

Concept / Approach:
Partition the timeline into three intervals based on X2: before overlap, during overlap, and after overlap (while X1 is still HIGH). Evaluate XOR in each interval using the one-HIGH-only condition.

Step-by-Step Solution:

Verification / Alternative check:
Constructing a quick timing diagram or tabulating values at the boundary points t = 0, 20, 35, 75 confirms the pulse widths and the separation. No other transitions occur since inputs are constant outside these boundaries.

Why Other Options Are Wrong:

• Option B: Claims a 15 µs pulse in the output; during 20–35 µs both inputs are HIGH, so XOR must be 0 (a gap), not a pulse.
• Option C: Omits the initial 20 µs pulse that occurs before the overlap.
• Option D: Adds an extra 15 µs output pulse that does not exist; the 15 µs is the LOW gap during overlap.

Common Pitfalls:
Confusing the overlap interval as producing an XOR high; miscounting widths; or forgetting to include the post-overlap tail while X1 remains HIGH.

Final Answer:
The exclusive-OR output is a 20 µs pulse followed by a 40 µs pulse, with a separation of 15 µs between the pulses.