Leakage in real capacitors – equivalent circuit representation A practical (leaky) capacitor is often modeled by an ideal capacitance C in parallel with a finite resistance R representing leakage. Is this representation correct?

Introduction / Context:
Real capacitors are not perfect: insulation resistance is finite, meaning a small DC current can flow through the dielectric. Circuit models capture this “leakage” to predict long-term charge retention, RC timing accuracy, and power loss.

Given Data / Assumptions:

• Small-signal circuit modeling at low to moderate frequencies.
• Dominant DC leakage path through dielectric approximated as a resistor.
• Other parasitics (ESR, ESL) neglected for simplicity here.

Concept / Approach:

The simplest leaky-capacitor model is an ideal C in parallel with a large R (insulation resistance). Under DC, the capacitor branch is open while the resistor passes a small steady leakage current; under AC, the capacitive branch dominates reactively. This parallel model correctly predicts voltage droop on hold circuits and long time-constant behavior in integrators and sample-and-hold systems.

Step-by-Step Solution:

Verification / Alternative check:

Dielectric-loss models using complex permittivity map to a parallel RC admittance where G = 1/R captures in-phase loss current; this is consistent with the simple parallel representation for leakage.

Why Other Options Are Wrong:

(b) contradicts standard practice; (c) the model is useful at DC and low frequency; (d) leakage exists across many capacitor types, not only electrolytics; (e) a series R models ESR, not dielectric leakage.

Common Pitfalls:

Confusing ESR (series loss affecting ripple and heating) with leakage (parallel loss affecting DC hold); ignoring temperature and voltage dependence of leakage resistance.

Final Answer:

True