Making a D flip-flop toggle like a T flip-flop: Which connection forces a clocked D flip-flop to change state (toggle) on every qualifying clock edge?

Introduction / Context:
A D (data) flip-flop copies its D input to Q on the active clock transition, subject to setup and hold times. A common technique is to turn a D flip-flop into a T (toggle) flip-flop. This is useful for building divide-by-2 counters and frequency dividers with minimal hardware.

Given Data / Assumptions:

• The D flip-flop updates Q with the value present at D at the active clock edge.
• Connections may include feedback from Q or Q̅ to D.
• We seek a configuration that guarantees Q switches state each clock.

Concept / Approach:
If the D input always receives the complement of the current output, then at the next clock edge Q must change to the opposite value. The simplest way to enforce this is to connect Q̅ (the inverted output) directly to D. If Q̅ is 1, D is 1 and Q becomes 1 at the next edge; if Q̅ is 0, D is 0 and Q becomes 0 at the next edge. Because Q toggles at each qualifying edge, the flip-flop behaves like a T-FF with T implicitly at logic 1.

Step-by-Step Solution:

Verification / Alternative check:
Simulate the flip-flop with D = Q̅; you will observe Q toggling on every active edge, producing a 50% duty cycle square wave at half the input clock frequency (assuming symmetric timing).

Why Other Options Are Wrong:

Common Pitfalls:
Neglecting setup/hold timing or using the wrong clock edge; forgetting that asynchronous clears/presets override the toggling behavior.

Final Answer:
Connect Q̅ (the complemented output) back to D