Maintaining reset on a J-K flip-flop through a clock event: A J-K flip-flop is currently reset and must remain reset after the next active clock edge. Which input condition guarantees that Q stays LOW?

Introduction / Context:
The J-K flip-flop generalizes the S-R and T flip-flops. Its truth table shows how inputs J and K control setting, resetting, holding, and toggling on each clock edge. Ensuring that a reset condition persists through a clock requires choosing inputs that force Q to remain LOW.

Given Data / Assumptions:

• Edge-triggered J-K flip-flop with synchronous control via J and K.
• Initial state: Q = 0 (reset).
• We want Q to remain 0 after the next clock event.

Concept / Approach:
The canonical J-K table indicates: J = 0, K = 0 → hold; J = 0, K = 1 → reset; J = 1, K = 0 → set; J = 1, K = 1 → toggle. Starting from Q = 0, both hold and reset rows preserve LOW. However, to guarantee staying reset even if transiently disturbed or to enforce reset from an unknown state, the unambiguous forcing condition is J = 0 and K = 1, which actively drives Q to 0 on the clock.

Step-by-Step Solution:

Verification / Alternative check:
Compare to the hold case (J = 0, K = 0): it preserves the current state but does not force reset if noise or an earlier error had set Q. The reset case is more definitive for ensuring LOW output.

Why Other Options Are Wrong:

Common Pitfalls:
Confusing the hold and reset actions; applying J = K = 1 which toggles and can break the required condition.

Final Answer:
J = 0 and K = 1