In the circuit below, delay of the EXOR and AND Logic gates are 20 μs and 10 μs respectively, then the wave y' and y (with initial condition y = 1) will be :

Since y is at logic '1' initially, y' must be at logic '1'.

Also, one input of the EXOR gate is tied to zero therefore 'f' will be directly transferred to the output.

The logic gates will introduce gate delays which will lead to the answer .