Which is not an output state for tristate logic?

More Questions from Integrated Circuit Technologies

• A TTL NAND gate with IIH(max) of 40 µA per input drives ten TTL inputs. How much current does the drive output source?
• An open-drain gate is the CMOS counterpart of ________.
• Which factor does not affect CMOS loading?
• A certain gate draws 1.8 µA when its output is HIGH and 3.3 µA when its output is LOW. VCC is 5 V and the gate is operated on a 50% duty cycle. What is the average power dissipation (PD)?
• One output structure of a TTL gate is often referred to as a ________.
• The nominal value of the dc supply voltage for TTL and CMOS is ________.
• If ICCH is specified as 1.1 mA when VCC is 5 V and if the gate is in a static (noncharging) HIGH output state, the power dissipation (PD) of the gate is ________.
• Which is not a precaution for handling CMOS?
• Unused TTL inputs should be tied LOW.
• There are four different logic level ranges for TTL and CMOS: VIL, VIH, VOL, and VOH.

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