CMOS outputs: An open-drain CMOS gate is the direct counterpart of which TTL output style?

Introduction / Context:
Output structures in logic families often have analogous forms. In CMOS, the “open-drain” configuration mirrors the TTL “open-collector.” Understanding this equivalence is important for bus wiring, wired-AND/OR functions, and level translation using pull-up resistors.

Given Data / Assumptions:

• Open-drain CMOS exposes the drain of an NMOS to the pin; it can pull LOW but not drive HIGH.
• Open-collector TTL exposes the collector of an NPN; it can pull LOW but not drive HIGH.
• Both require an external pull-up to generate a logic HIGH.

Concept / Approach:
Because both topologies only sink current, they are interchangeable conceptually. Using a resistor to VCC, the line idles HIGH. Multiple outputs can be “wire-ORed” (wired-AND in active LOW logic) on a shared bus. Rise time depends on the pull-up and bus capacitance, so resistor sizing is critical.

Step-by-Step Solution:
Identify the CMOS structure: open-drain.Identify the TTL analog: open-collector.Conclude they are counterparts requiring a pull-up for HIGH.

Verification / Alternative check:
Examine datasheets: both specify VOL at a sink current, but VOH depends on the external pull-up, not an internal transistor.

Why Other Options Are Wrong:
Tristate TTL can actively drive HIGH/LOW or Hi-Z, unlike open structures.ECL and BJT entries describe different logic paradigms, not open-sink outputs.

Common Pitfalls:
Forgetting to add a pull-up; without it, the output floats and may never reach a valid logic HIGH level.

Final Answer:
an open-collector TTL gate