Average power in a digital gate (50% duty) A gate draws 1.8 µA when the output is HIGH and 3.3 µA when the output is LOW. With VCC = 5 V and a 50% duty cycle, what is the average power dissipation (PD)?

Introduction / Context:
Digital CMOS and TTL families specify supply current in different logic states. Average power dissipation over time depends on the time spent in each state. Here, we compute average current over a 50% duty cycle and multiply by supply voltage.

Given Data / Assumptions:

• I_H (HIGH-state current) = 1.8 µA.
• I_L (LOW-state current) = 3.3 µA.
• Duty cycle = 50% HIGH, 50% LOW.
• VCC = 5 V. Ignore dynamic switching losses for this simple estimate.

Concept / Approach:
Average current is the time-weighted mean of state currents. With equal time in both states, I_avg = (I_H + I_L) / 2. Average power PD_avg = VCC * I_avg.

Step-by-Step Solution:
I_avg = (1.8 µA + 3.3 µA) / 2 = 2.55 µA.PD = VCC * I_avg = 5 V * 2.55 µA.PD = 12.75 µW.

Verification / Alternative check:
Because the duty cycle is symmetric, arithmetic mean is valid. If the duty cycle were not 50%, a weighted average would be used.

Why Other Options Are Wrong:
2.55 µW: mistakenly multiplies current average by 1 V or omits VCC.1.27 µW and 5 µW: arithmetic/units errors.5 µW is a round number guess with no basis here.

Common Pitfalls:
Forgetting to multiply by VCC, mixing µA with mA, or ignoring dynamic (capacitive) power when edge rates are high (not required in this static-state problem).

Final Answer:
12.75 µW