Wiring a 7493 as a MOD-12 (divide-by-12) counter Which pins of the 7493 should be connected together to configure the counter for modulus 12 operation?

Introduction / Context:
The 7493 is a 4-bit ripple counter with separate divide-by-2 and divide-by-8 sections. By wiring its outputs back to the asynchronous reset inputs, you can truncate the natural modulus-16 sequence to achieve a desired modulus such as 12 (counts 0 through 11). Correct pin connections are crucial to reset the counter exactly at the intended terminal count.

Given Data / Assumptions:

• Pin roles (TTL 7493): QA=12, QB=9, QC=8, QD=11.
• CLK B (higher stages) = pin 1; CLK A (LSB) = pin 14.
• Asynchronous reset inputs: R01=2 and R02=3; both must be HIGH to clear.
• Goal: MOD-12 → reset at binary 1100 (decimal 12), i.e., QC=1 and QD=1.

Concept / Approach:
First, connect QA (pin 12) to CLK B (pin 1) so the higher stages count at QA/2, creating a standard 4-bit chain. To force modulus 12, detect count 12 (QD=1 and QC=1) and feed those signals to the two reset pins so that when the state reaches 1100, the counter asynchronously clears to 0000 on the very next instant.

Step-by-Step Solution:

Verification / Alternative check:
List the count sequence and confirm that upon reaching 1100 both reset pins go HIGH, instantly clearing the counter to 0000, yielding exactly 12 distinct states per cycle.

Why Other Options Are Wrong:

• 12 to 1, 11 to 3, 9 to 2: Uses QB instead of QC; would reset at 1010 (10), not 12.
• 12 to 1, 11 to 3, 12 to 2: Misuses QA for a reset input and breaks the chain.
• 12 to 1, 11 to 3, 1 to 2: Feeding the clock into reset is incorrect and unstable.

Common Pitfalls:
Forgetting both reset inputs must be asserted together; mixing up QC and QB pin numbers; or omitting the QA→CLK B link so upper stages never count.

Final Answer:
12 to 1, 11 to 3, 8 to 2