Curioustab
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Home
»
Digital Electronics
»
Counters
A principle regarding most display decoders is that when the correct input is present, the related output will switch:
HIGH
to high impedance
to an open
LOW
Correct Answer:
LOW
← Previous Question
Next Question→
More Questions from
Counters
Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
What function will the counter shown below be performing during period "B" on the timing diagram?
Any divide-by-N counter can be formed by using external gating to ________ at a predetermined number.
The terminal count of a modulus-11 binary counter is ________.
Which of the following is an example of a counter with a truncated modulus?
Which of the following procedures could be used to check the parallel loading feature of a counter?
Referring to the given figure, what causes the Control FF to reset after D7?
The circuit given below has no output on Q1 when examined with an oscilloscope. All J-K inputs are HIGH, the CLK signal is present, and the Q0 is toggling. The C input of FF1 is a constant LOW. What could be causing the problem?
Which segments (by letter) of a seven-segment display need to be active in order to display a digit 6?
For a multistage counter to be truly synchronous, the ________ of each stage must be connected to ________.
Discussion & Comments
No comments yet. Be the first to comment!
Name:
Comment:
Post Comment
Join Discussion
Discussion & Comments