S-R NOR latch behavior: When both S and R inputs are driven HIGH, the output of an S–R NOR latch is “unpredictable.” Choose the best evaluation.

Introduction / Context:
S–R latches are the foundation of many storage elements. Knowing the “forbidden” input condition and its impact on output validity is vital when designing debouncers and state machines.

Given Data / Assumptions:

• Latch type: S–R built from NOR gates.
• Inputs S and R are simultaneously driven HIGH.
• We consider steady-state behavior and subsequent release.

Concept / Approach:
For an S–R NOR latch, S = 1 and R = 1 force both NOR outputs low (Q = 0 and Q̄ = 0), which violates the complementary relationship. When the inputs are released (pulled low), internal propagation and any skew can cause either side to dominate, so the subsequent state is indeterminate. Therefore, the condition is called “forbidden” or “invalid,” often summarized as yielding an unpredictable outcome.

Step-by-Step Solution:

Verification / Alternative check:
Textbooks note that S = R = 1 is forbidden for NOR latches (and S = R = 0 is forbidden for NAND latches), exactly because the next state after release is indeterminate.

Why Other Options Are Wrong:
Incorrect: Ignores the indeterminate resolution after release.

Applies only to NAND latches / only at power-up: The forbidden-state concept is general; the specific input combination differs for NAND vs NOR realizations.

Common Pitfalls:
Assuming unpredictability means “random during the high-high interval.” During S = R = 1 both outputs are known low; the unpredictability refers to the final state after inputs are deasserted.

Final Answer:
Correct