Master–slave J–K flip-flop toggle condition: When J = K = 1, Q and Q̅ will switch to their __________ state(s) at the _____________________. Choose the most accurate completion.

Introduction / Context:
The J–K flip-flop generalizes the S–R flip-flop and avoids its forbidden state. One hallmark is the “toggle” condition when both J and K are asserted. Accurately stating when Q toggles is essential to prevent race-around issues and to interpret timing diagrams correctly, especially in master–slave organizations.

Given Data / Assumptions:

• Master–slave J–K flip-flop.
• J = K = 1 (toggle condition).
• “Active clock edge” refers to whichever edge the device is specified to accept (rising or falling).

Concept / Approach:
With J = K = 1, the J–K flip-flop complements its present state at each active clock edge. In a master–slave configuration, the master captures on one phase and the slave updates on the opposite phase, but from a black-box perspective the external output Q toggles at the specified active edge. Thus, Q and Q̅ move to their opposite states synchronously with that edge.

Step-by-Step Solution:

Verification / Alternative check:
Examine vendor timing diagrams for classic master–slave J–K devices; they show Q updating to the complement at each valid edge when J=K=1, confirming the statement.

Why Other Options Are Wrong:

• Inverted, positive clock edge: Overly specific; also “inverted” is ambiguous versus “opposite.”
• Quiescent, negative clock edge: “Quiescent” is incorrect under toggling; edge polarity is device dependent.
• Reset, synchronous clock edge: Reset is not implied by J = K = 1.
• Unchanged, trailing edge only: Contradicts toggle behavior.

Common Pitfalls:
Assuming toggle occurs throughout a high level (race-around). True edge-triggered or master–slave designs confine the update to the clock edge, preventing race-around when designed correctly.

Final Answer:
opposite, active clock edge