S–R NAND latch behavior with both inputs asserted LOW: For an S–R latch implemented with cross-coupled NAND gates, when both S and R inputs are LOW simultaneously, what is the output state?

Introduction / Context:
S–R latches can be built from cross-coupled NAND or NOR gates, and the “active” level of S and R depends on the gate type. Understanding the illegal/forbidden input combination and the immediate output levels prevents design mistakes when using basic memory elements or debouncing circuits.

Given Data / Assumptions:

• S–R latch constructed from two NAND gates (active-LOW inputs).
• Both inputs are driven LOW at the same time (S = 0, R = 0).
• Outputs are the usual Q and Q̅.

Concept / Approach:
For a NAND gate, any input at 0 forces the output to 1 regardless of the other input. With both S and R LOW simultaneously, each NAND gate sees a 0 at one input, so both outputs are forced HIGH. This is the “forbidden” (invalid) state because Q and Q̅ become 1 simultaneously, violating the requirement that they be complements. Upon releasing S and R back to 1, the latch may settle unpredictably. However, while S = 0 and R = 0 are applied, each output level is HIGH.

Step-by-Step Solution:

Verification / Alternative check:
Write the NAND truth rule: Y = NOT(A * B). With A = 0, Y = NOT(0) = 1 regardless of B. Symmetry on both gates confirms both outputs are 1 when S = R = 0.

Why Other Options Are Wrong:

• LOW: Contradicts NAND forcing behavior with a 0 input.
• Unpredictable/Floating/Metastable: These may describe the state after releasing inputs, but the instantaneous enforced level with both inputs LOW is HIGH at both outputs.

Common Pitfalls:
Mixing NAND and NOR latch conventions; forgetting that the “forbidden” term refers to the logical validity and subsequent uncertainty, not the immediate gate-level output when both inputs are asserted.

Final Answer:
HIGH