Race-around versus invalid-state: “The J–K flip-flop eliminates the RACE problem when both J and K inputs are HIGH.” Provide the most accurate evaluation.

Introduction / Context:
The J–K flip-flop improves upon the S–R by allowing J = K = 1 without an “invalid” state; however, the separate issue of race-around can still occur in level-triggered designs. This question distinguishes those concepts.

Given Data / Assumptions:

• Inputs J and K may both be HIGH.
• We consider both level-triggered and edge-triggered JK implementations.
• Clock pulse width may be long relative to internal propagation delay.

Concept / Approach:
With J = K = 1, a JK flip-flop toggles its state. In a level-triggered device, a long clock gate can allow multiple toggles within a single clock pulse (race-around). This is not “eliminated” by the JK function itself. Edge-triggered or master–slave JK designs constrain the sampling window to an edge or short internal pulse, thereby avoiding race-around. Thus, the blanket claim is incorrect.

Step-by-Step Solution:

Verification / Alternative check:
Textbook timing diagrams show race-around in level-triggered JK. Device datasheets for edge-triggered JK explicitly advertise “no race-around.”

Why Other Options Are Wrong:
Correct: Confuses “no invalid state at J = K = 1” with “no race-around.”

Only true at low frequencies: A long clock pulse can still exceed internal delays even at low frequency; the issue is pulse width, not clock rate alone.

Common Pitfalls:
Assuming JK inherently solves all timing hazards. Triggering method matters as much as logic function.

Final Answer:
Incorrect