RC pulse response with duty cycle — a repetitive rectangular pulse (50% duty) is applied to the input of an RC “integrator.” If one time constant τ is less than one-fifth of the pulse width (τ < PW/5), will the capacitor be able to essentially charge and discharge to its final values each half-cycle (i.e., reach ≈99% within 5τ)?

Difficulty: Easy

Correct Answer: Correct

Explanation:


Introduction / Context:
An RC “integrator” is simply an RC network driven by a pulse or step where the output of interest is usually taken across the capacitor. Whether it truly integrates or instead reaches near steady states during each pulse depends on the relationship between the time constant τ = R * C and the pulse width (PW) and duty cycle. This question asks if a capacitor can effectively charge and discharge to its final values within each half-cycle when τ is less than one-fifth of the pulse width in a 50% duty train.


Given Data / Assumptions:

  • Input: repetitive pulse, 50% duty (high time = low time = PW/2 if period = PW).
  • RC network with time constant τ = R * C.
  • “Fully” or “completely” is interpreted in practical design sense as ≈99% settling by about 5τ.
  • Ideal source and components for first-order analysis; no loading beyond the RC itself.


Concept / Approach:
First-order exponentials settle to about 63% in 1τ, 86% in 2τ, 95% in 3τ, 98% in 4τ, and 99.3% in 5τ. Thus, when a pulse high (or low) interval exceeds roughly 5τ, the capacitor will reach within about 1% of its final value for that interval. With a 50% duty waveform, there is a charging interval and a discharging interval of the same length; the same 5τ rule applies to both halves.


Step-by-Step Solution:

Relate settling to time constant: ≈5τ → 99% of final value.Given τ < PW/5, the pulse high time (PW/2) is > 2.5τ, and if PW is defined as the high duration itself, then τ < PW/5 means 5τ < PW, satisfying the 99% criterion.Apply the same logic to the low interval (50% duty → equal time for discharge).Conclude the capacitor essentially charges and discharges each half-cycle under the stated inequality.


Verification / Alternative check:
Use v_C(t) = V_final + (V_initial − V_final) * exp(−t/τ). For t = 5τ, |v_C − V_final| ≈ 0.7% of the step. With τ < PW/5, t ≥ 5τ within each interval, yielding ≈99% settling.


Why Other Options Are Wrong:

  • Incorrect / depends only on duty cycle: settling depends primarily on τ relative to the interval length, not duty alone.
  • Only if AC-coupled or R = C: irrelevant to the exponential time constant rule.


Common Pitfalls:
Confusing “integrator behavior” (which prefers τ ≫ PW) with “full charging” (which needs τ ≪ PW). The same RC can show either behavior depending on τ vs. PW.


Final Answer:
Correct — with τ < PW/5, the capacitor essentially reaches its final value each half-cycle.

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