Write-cycle control signals in RAM: A typical static or dynamic RAM writes (stores data internally) only when the chip-select (CS) is active and the write-enable (WE) signal is also active for a write, according to the device’s active level. Evaluate the claim: "A typical RAM will write whenever CS is active and WE is inactive."

Introduction / Context:
Random-access memory devices control read and write behavior via chip-select (CS), write-enable (WE), and output-enable (OE) signals. Correctly understanding their active levels prevents accidental overwrites and bus conflicts.

Given Data / Assumptions:

• Typical RAMs use active-LOW control pins labeled /CS, /WE, /OE.
• “Active” means the asserted level (often LOW).
• Write occurs only when both the device is selected and WE is asserted for writing.

Concept / Approach:
For active-LOW controls: to write, /CS = 0 and /WE = 0 during the valid address/data window. If /WE is inactive (i.e., HIGH for active-LOW WE), the device does not perform a write; it typically either reads (if /OE is active) or remains deselected/high-impedance. Thus the statement claiming writing when WE is inactive is incorrect.

Step-by-Step Solution:
1) Identify control polarity from the datasheet: /CS, /WE, /OE.2) Write truth: write = (/CS asserted) AND (/WE asserted) with proper timing.3) Read truth: read = (/CS asserted) AND (/OE asserted) AND (/WE deasserted).4) Conclude that an inactive WE prevents writing, invalidating the claim.

Verification / Alternative check:
Timing diagrams explicitly show write-cycle waveforms where /WE goes active for a defined pulse width while addresses and data meet setup/hold times.

Why Other Options Are Wrong:
“Correct” reverses the necessary WE polarity. References to ROM or OE do not change the fundamental requirement that WE be asserted for writes.

Common Pitfalls:
Mixing up active-high vs active-low naming; neglecting setup/hold windows; assuming CS alone controls writes.

Final Answer:
Incorrect