DRAM addressing technique: Dynamic memories such as the classic 2118 16K × 1 RAM multiplex the address bus into row and column portions to reduce pin count. Evaluate the correctness of this statement.

Introduction / Context:
Dynamic RAM achieves high density by arranging cells in arrays addressed by row and column. To limit package pins, DRAM devices multiplex the address bus: the same pins carry row addresses during one phase and column addresses during another, strobed by RAS and CAS signals.

Given Data / Assumptions:

• A legacy example is the 2118 16K × 1 device.
• Address multiplexing reduces pin count compared to providing separate row and column pins simultaneously.
• Timing uses RAS (row address strobe) and CAS (column address strobe).

Concept / Approach:
On a memory access, the controller first places the row address on the address pins and asserts RAS to latch it. Next, it places the column address on the same pins and asserts CAS to latch the column. Internally, sense amps select the correct cell(s). This technique is universal to mainstream DRAM generations (FPM, EDO, SDR, DDR families) though details vary.

Step-by-Step Solution:
1) Present row address → assert RAS to capture it.2) Present column address → assert CAS to capture it.3) DRAM core accesses cell(s) at [row, column].4) Data is read or written according to the cycle type.

Verification / Alternative check:
Timing diagrams in DRAM datasheets explicitly show row/column multiplexing; SDR/DDR data sheets maintain the RAS/CAS naming convention conceptually (even as signaling evolves).

Why Other Options Are Wrong:
“Incorrect” disagrees with standard DRAM operation. SRAM does not use row/column multiplexing; its arrays are accessed without RAS/CAS strobes. “CAS precedes RAS” refers to a specific refresh mode, not normal addressing.

Common Pitfalls:
Confusing DRAM’s multiplexed external addressing with internal bank/row/column abstractions in modern DDR; the multiplexing principle remains.

Final Answer:
Correct