Fuse semantics in PLDs (AND/OR arrays): Consider how “blown” versus “intact” fuses affect connectivity in programmable AND/OR planes. Is it correct to claim: “A blown fuse at an OR gate is a LOW, and a blown fuse at an AND gate is a HIGH” as a universal rule?

Introduction / Context:
Programmable Logic Devices implement sum-of-products logic using programmable interconnects in AND/OR arrays (for example, PLA, PAL, PROM). Fuses (or antifuses/EEPROM links) determine whether a literal connects to a product term or whether a product term connects to an OR output. Understanding what a “blown” fuse means is about connectivity, not an absolute HIGH or LOW logic level at a gate.

Given Data / Assumptions:

• Fuse state controls presence/absence of a connection.
• AND plane connections include literals or their complements; absence yields don’t-care for that literal.
• OR plane connections sum selected product terms; absence means that term does not contribute.

Concept / Approach:
In classical fuse-based PLDs, an intact fuse implies a connection; a blown fuse removes it. This does not directly translate to a literal HIGH or LOW level. In the AND array, including a literal constrains the product term; removing it produces a don’t-care (neither forced HIGH nor forced LOW). In the OR array, removing a product-term connection simply means that term does not feed the OR sum. Therefore, the statement that a blown fuse “is LOW” in one plane and “is HIGH” in the other is an oversimplification and is not a universal rule.

Step-by-Step Solution:

Verification / Alternative check:
Reference any PLA/PAL fuse map description: the programming matrix shows presence/absence of connections, not fixed logic levels at the logic gates.

Why Other Options Are Wrong:

Common Pitfalls:
Assuming removing a literal forces a term HIGH; ignoring that “don’t-care” broadens the minterm rather than driving a constant level.

Final Answer:
Incorrect