Difficulty: Easy
Correct Answer: Correct
Explanation:
Introduction / Context:
JTAG (IEEE 1149.1) defines a standard boundary-scan architecture and a serial test access port (TAP). The TAP enables testing, programming, and debugging through a small set of well-known signals used on PLDs, FPGAs, microcontrollers, and ASICs.
Given Data / Assumptions:
Concept / Approach:
The TAP controller is a defined state machine advanced by TCK and TMS. TDI and TDO form the serial data path through the instruction and data registers. Many devices also implement optional TRST (Test Reset). These signal names are standardized in the specification and appear consistently in datasheets and programming cables.
Step-by-Step Solution:
Verification / Alternative check:
Vendor boundary-scan descriptions and programming cables label these signals consistently. IEEE 1149.1 documentation uses these exact names.
Why Other Options Are Wrong:
Common Pitfalls:
Confusing TAP with SPI; miswiring TMS/TCK and preventing chain detection; ignoring pull-ups recommended on TMS/TDI.
Final Answer:
Correct
Discussion & Comments