Architecture insight: A master–slave JK flip-flop can be viewed structurally as a cascade of which underlying latch types?

Introduction / Context:
Understanding how complex flip-flops are built from simpler latches clarifies timing behavior, setup/hold requirements, and why certain race conditions are avoided. The master–slave JK is a pedagogical staple for this reason.

Given Data / Assumptions:

• JK functionality is implemented using level-sensitive latching stages.
• Master and slave operate on opposite clock levels.
• Internal gating prevents invalid S=R=1 conditions typical of a basic SR latch.

Concept / Approach:
The canonical construction uses two gated SR latches in series. The first (master) captures input information while the clock is high; the second (slave) updates the output when the clock is low. Feedback networks around the J and K pins translate JK semantics to valid S and R drive signals for the latches.

Step-by-Step Solution:
Identify basic building block: gated SR latch.Arrange two latches master→slave with complementary enables.Add gating so J/K requests translate into S/R pulses safely.Conclude structural view: two gated SR latches.

Verification / Alternative check:
Timing diagrams of the JK master–slave show level transparency phases consistent with SR latch behavior under gating.

Why Other Options Are Wrong:
SR + T / SR + D / two T / JK + T: none match the standard internal construction.

Common Pitfalls:
Equating master–slave flip-flops with true edge-triggered designs; overlooking the gating that maps JK inputs to safe SR controls.

Final Answer:
two gated SR latches (master and slave)