Introduction / Context:
Comparators are fundamental building blocks in analog and mixed-signal electronics. An ideal comparator compares an input voltage against a reference and outputs a saturated high or low level depending on the sign of the instantaneous difference. This question examines how a zero-DC sinusoidal input influences the duty cycle at the output when the reference (threshold) is set at 0 V.
Given Data / Assumptions:
- Input is a sine wave with amplitude 4 V (8 V peak-to-peak) and no DC component.
- Reference threshold is 0 V (the inverting or non-inverting input tied to ground, as in many textbook comparators).
- Comparator is ideal: infinite gain, zero propagation delay, and rail-to-rail saturated output levels.
Concept / Approach:
The duty cycle is the fraction of the period during which the output is high. For an ideal comparator with zero threshold, the output is high whenever the input is greater than 0 V and low whenever the input is less than 0 V. With a pure sine wave centered at 0 V, the time spent above and below zero in each cycle is exactly equal.
Step-by-Step Solution:
Let v_in(t) = 4 * sin(ωt). The comparator outputs HIGH when v_in(t) > 0 and LOW when v_in(t) < 0.Over one period T, sin(ωt) > 0 for exactly T/2 and < 0 for exactly T/2.Therefore, duty cycle D = (time HIGH) / T = (T/2) / T = 1/2.
Verification / Alternative check:
Zero crossings occur at ωt = 0, π, 2π, … . Between 0 and π, the sine is positive; between π and 2π, it is negative. The intervals are equal, confirming 50% duty.
Why Other Options Are Wrong:
1/3, 1/6, 1/12: These would require a DC offset shifting the zero-crossing angles or a non-sinusoidal input. With zero DC, symmetry forces 50% duty.'None of these': Incorrect because 1/2 is achievable and correct.
Common Pitfalls:
Confusing comparators with Schmitt triggers (which add hysteresis). Hysteresis or DC offset would change the duty cycle; a pure zero-centered sine with zero threshold yields 50%.
Final Answer:
1/2
Discussion & Comments