VHDL/HDL PROCESS semantics: Within a PROCESS, VARIABLES are considered to update ________ as statements execute, whereas SIGNALS referenced inside the same PROCESS update when the PROCESS ________.

Difficulty: Medium

Correct Answer: Immediately, suspends

Explanation:


Introduction / Context:
In VHDL (and similarly in many HDL teaching contexts), SIGNALS and VARIABLES have different update semantics. Misunderstanding this distinction is a common source of simulation mismatches and timing bugs. Knowing when each is updated helps you write predictable synchronous and combinational processes.


Given Data / Assumptions:

  • We are discussing code inside a single PROCESS.
  • VARIABLE assignments take effect immediately for subsequent statements in the same PROCESS activation.
  • SIGNAL assignments schedule updates that become effective when the PROCESS suspends (e.g., after wait/event) and resumes in the next delta cycle.


Concept / Approach:
A VARIABLE is local to the PROCESS and behaves like a software variable: when you assign to it, the new value is used by the next statement in that PROCESS activation. A SIGNAL represents a hardware wire/register; assigning to it does not instantly change its value for the remainder of that activation. Instead, the new value is queued and applied at PROCESS suspension, ensuring deterministic delta-cycle behavior and preventing races among concurrent statements in different processes.


Step-by-Step Solution:

Inside PROCESS: variable := new_value → next statement sees the new variable value immediately.Inside the same PROCESS: signal <= new_value → next statement still sees the old signal value until the PROCESS suspends.On suspension (e.g., end of PROCESS sensitivity or wait), scheduled signal updates take effect together.


Verification / Alternative check:
Simulate a simple counter where a variable accumulates sum and then assigns to a signal at the end of the PROCESS. Watch waveforms: the signal updates at suspension; intermediate variable changes are not visible outside until the final signal assignment posts.


Why Other Options Are Wrong:

  • “Once, starts” / “Twice, ends” / “Never, starts”: These do not reflect actual VHDL semantics.
  • “Immediately, resets”: Signals do not wait for a reset; they update at suspension/delta cycle.


Common Pitfalls:
Expecting signals to change immediately inside the PROCESS; chaining multiple signal assignments and assuming earlier ones are visible to later lines; forgetting that variables are not visible outside the PROCESS unless copied to signals.


Final Answer:
Immediately, suspends

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