Difficulty: Medium
Correct Answer: Immediately, suspends
Explanation:
Introduction / Context:
In VHDL (and similarly in many HDL teaching contexts), SIGNALS and VARIABLES have different update semantics. Misunderstanding this distinction is a common source of simulation mismatches and timing bugs. Knowing when each is updated helps you write predictable synchronous and combinational processes.
Given Data / Assumptions:
Concept / Approach:
A VARIABLE is local to the PROCESS and behaves like a software variable: when you assign to it, the new value is used by the next statement in that PROCESS activation. A SIGNAL represents a hardware wire/register; assigning to it does not instantly change its value for the remainder of that activation. Instead, the new value is queued and applied at PROCESS suspension, ensuring deterministic delta-cycle behavior and preventing races among concurrent statements in different processes.
Step-by-Step Solution:
Verification / Alternative check:
Simulate a simple counter where a variable accumulates sum and then assigns to a signal at the end of the PROCESS. Watch waveforms: the signal updates at suspension; intermediate variable changes are not visible outside until the final signal assignment posts.
Why Other Options Are Wrong:
Common Pitfalls:
Expecting signals to change immediately inside the PROCESS; chaining multiple signal assignments and assuming earlier ones are visible to later lines; forgetting that variables are not visible outside the PROCESS unless copied to signals.
Final Answer:
Immediately, suspends
Discussion & Comments