For a gated S–R flip-flop, the device enters the SET state when S = 1, R = 0, and the enable input EN = 1 (gate open). Evaluate this operating statement.

Introduction / Context:
The gated S–R flip-flop (often built from cross-coupled NAND or NOR gates) includes an enable input that allows S and R to affect the latch only when the gate is active. Understanding the truth conditions avoids indeterminate or race states.

Given Data / Assumptions:

• Enable EN is active-HIGH.
• Inputs S and R are level-sensitive while EN = 1.
• Illegal condition S = R = 1 is avoided for NOR-based implementation (or S = R = 0 for NAND-based).

Concept / Approach:
With EN = 1, the S input requests Q to go HIGH (SET) and the R input requests Q to go LOW (RESET). If S = 1 and R = 0 while enabled, the latch must set. When EN = 0, the latch holds its previous state regardless of S and R levels.

Step-by-Step Solution:

Verification / Alternative check:
Gate-level truth tables of common S–R latches show the same condition for SET when enabled. Timing diagrams also confirm Q rises under these inputs.

Why Other Options Are Wrong:
Active-LOW enable would invert the gating rule but not this fundamental SET condition when interpreted correctly. Edge-triggering pertains to flip-flops built from master–slave latches; a gated S–R latch is level-enabled, not edge-triggered.

Common Pitfalls:
Mixing NAND versus NOR implementations and their active levels, or driving the forbidden input combination that can cause metastability.

Final Answer:
Correct