Practical resolution limit of a binary-weighted resistor DAC: up to how many bits is this approach generally feasible before resistor ratio spread becomes impractical?

Introduction / Context:Binary-weighted resistor DACs require resistor values in powers of two. As resolution increases, the ratio between the smallest and largest resistors grows quickly, stressing tolerance, temperature tracking, and switch on-resistance requirements. This item asks for the commonly cited practical upper limit in bits.

Given Data / Assumptions:

• Binary-weighted topology (R, 2R, 4R ... 2^(n-1)R).
• General-purpose, discrete or monolithic resistors with realistic tolerances.
• Focus on practical, economical implementation rather than extreme custom trimming.

Concept / Approach:The resistor spread grows exponentially with resolution. For 8 bits, the largest element is 128R relative to the least significant bit branch. Beyond around 8 bits, achieving low integral and differential nonlinearity with untrimmed parts becomes hard and expensive. Hence designers typically shift to R/2R ladders for higher resolution.

Step-by-Step Solution:

Verification / Alternative check:Reference application notes consistently recommend R/2R ladders at or above 8 bits due to manufacturability and linearity advantages.

Why Other Options Are Wrong:10 bits: possible only with tight trims, special processes; not generally practical.

2 bits / 4 bits: these are trivial and not a “limit.”

Common Pitfalls:Confusing absolute tolerance with ratio matching; the main issue is exponential spread across branches, not just nominal value accuracy.

Final Answer:8 bits