ADC conversion time behavior: which ADC type has a fixed conversion time that does not depend on the analog input value?

Introduction / Context:
Different analog-to-digital converter (ADC) architectures exhibit different timing behaviors. Some have conversion times that vary with the input, while others are constant. Selecting the right architecture often hinges on this property.

Given Data / Assumptions:

• Focus is the dependence (or independence) of conversion time on input level.
• Standard ADC architectures: successive approximation, dual-slope, flash, etc.
• We assume typical single-shot conversions.

Concept / Approach:
Successive approximation (SAR) ADCs perform a fixed number of comparison steps equal to the resolution in bits, so conversion time is essentially constant and independent of input value. Dual-slope converters integrate over a fixed period but are not presented correctly here as “Dual”; their timing is fixed but used primarily for noise rejection and precision—however, the best match to the phrasing and common exam focus is SAR. “Recessive approximation” is not a standard term.

Step-by-Step Solution:

Verification / Alternative check:
Typical SAR datasheets specify t_conv as a constant number of clock cycles, independent of input amplitude.

Why Other Options Are Wrong:
Substandard: not an architecture.

Dual: ambiguous wording; dual-slope exists but is not the expected answer here.

Recessive approximation: not a valid term.

Common Pitfalls:
Confusing architecture names; assuming conversion time variability is dominated by input amplitude in SAR (it is not).

Final Answer:
Successive approximation