An edge-triggered flip-flop changes state only under which condition related to its trigger (clock) input?

Introduction / Context:
Edge-triggered storage elements respond at the instant a clock transitions, not while it remains steady. This property allows precise timing in synchronous systems, enabling designers to coordinate state updates across many registers.

Given Data / Assumptions:

• We are considering an edge-triggered device (not a level-sensitive latch).
• The “trigger” refers to the clock input of the flip-flop.
• Edges may be rising or falling depending on the device symbol and configuration.

Concept / Approach:
Edge-triggering implies that data is sampled and state may change only at the moment the clock transits through its active edge. While the clock remains HIGH or LOW, further changes in D do not propagate to Q until the next active edge. This isolation reduces race and transparency issues common with level-sensitive elements.

Step-by-Step Solution:

Verification / Alternative check:
Timing diagrams and truth tables for D/JK flip-flops confirm state changes only on edges, provided setup/hold are satisfied and asynchronous controls are inactive.

Why Other Options Are Wrong:
“Trigger HIGH/LOW” describes level-sensitive behavior, not edge-triggering. “D input HIGH” confuses data value with timing; state changes can occur on edges regardless of whether D is 0 or 1 (subject to the device function).

Common Pitfalls:
Assuming that any clock activity while HIGH or LOW affects Q (that is true for latches, not edge-triggered flip-flops). Also, forgetting setup/hold can cause metastability, obscuring the apparent edge-triggered operation.

Final Answer:
the trigger input changes levels