NOR-gate S–R latch: deducing inputs from the outputs Given a cross-coupled NOR-gate S–R flip-flop has outputs Q = 0 and Q̄ = 1 (the stable reset state), determine the required S and R input levels.

Introduction / Context:
The cross-coupled NOR S–R latch is a fundamental memory element. Knowing one of its stable output states lets us infer which inputs could have produced or are maintaining that state. Here the outputs are Q = 0 and Q̄ = 1, which is the conventional reset state.

Given Data / Assumptions:

• Latch type: S–R using NOR gates, active-high inputs.
• Outputs observed: Q = 0 and Q̄ = 1.
• We seek steady-state inputs consistent with the observed outputs (not the transient drive used to reach it).

Concept / Approach:
For a NOR-based latch: a logic 1 on S forces Q = 1; a logic 1 on R forces Q = 0. When both S and R are 0, the latch holds the prior state. The illegal condition is S = R = 1 because both outputs would be 0, violating complementarity.

Step-by-Step Solution:
Given Q = 0 and Q̄ = 1, the state is RESET.A sufficient input combination to force this is R = 1 and S = 0 (R dominates Q to 0 via NOR gating).After the state is reached, R can be returned to 0 to hold; however, the question focuses on inputs that correspond to (or maintain) Q = 0 and Q̄ = 1.Thus, S = 0, R = 1 is the direct forcing combination.

Verification / Alternative check:
Truth behavior: NOR with R = 1 ensures its output (feeding Q) is 0 regardless of feedback; the complementary side remains 1, confirming Q̄ = 1.

Why Other Options Are Wrong:
“S = 1, R = 1” is invalid. “S = 1, R = 0” would set Q = 1. “S = 0, R = 0” simply holds the previous state but does not necessarily explain how Q became 0 if it were previously 1.

Common Pitfalls:
Confusing NOR and NAND latch polarities; overlooking that S = R = 0 is a hold, not a force, condition.

Final Answer:
S = 0, R = 1