For a J–K flip-flop with J = 1 and K = 1 applied before a valid clock edge, what will the next clock pulse cause the output to do?

Introduction / Context:
The J–K flip-flop generalizes the behavior of S–R and D flip-flops. When both J and K are asserted, the device enters a toggle mode, making it useful as a divide-by-2 counter stage or for state machines that require alternating outputs.

Given Data / Assumptions:

• Inputs J = 1, K = 1 are stable and satisfy setup/hold around the active clock edge.
• No asynchronous set/reset is active.
• Current output state Q is either 0 or 1 prior to the clock edge.

Concept / Approach:
The J–K truth table shows: J = 1, K = 0 → set; J = 0, K = 1 → reset; J = K = 0 → no change; J = K = 1 → toggle. Thus, each active edge in this condition complements the present state, creating a square wave at half the clock frequency at Q.

Step-by-Step Solution:

Verification / Alternative check:
Simulate successive clock edges with J = K = 1; observe Q sequence 0→1→0→1… if starting at 0 (or the inverse if starting at 1).

Why Other Options Are Wrong:
“set” and “reset” correspond to J = 1, K = 0 or J = 0, K = 1, not J = K = 1. “latch” implies level-sensitive behavior, not edge-triggered toggling on a J–K flip-flop.

Common Pitfalls:
Forgetting setup/hold can break toggle behavior. Also, wiring feedback to create a T flip-flop must ensure glitch-free J and K inputs.

Final Answer:
toggle