In VHDL structural design, each component instance is written using a label followed by a specific punctuation mark and then the referenced entity/architecture or library primitive name. Which punctuation mark correctly follows the instance label?

Introduction / Context:
Structural VHDL describes a circuit by instantiating components and wiring ports. The syntax uses labels to identify each instance. Remembering the exact punctuation after the label avoids compilation errors and improves code readability.

Given Data / Assumptions:

• A typical instantiation looks like: my_add: entity work.adder(rtl) port map(...);
• The label (my_add) identifies this occurrence in the design.
• After the label comes punctuation before the design unit reference.

Concept / Approach:
VHDL requires a colon after the instance label to separate it from the unit being instantiated (entity, component, or configuration). After the colon, the designer specifies the entity name, possibly with a library and architecture, followed by the port map association list and ending with a semicolon.

Step-by-Step Solution:

Verification / Alternative check:
Any VHDL reference or compiler error messages will complain if a semicolon or other token is used in place of the colon after the label.

Why Other Options Are Wrong:
“function” and “signal” are not punctuation. A semicolon terminates the entire instantiation statement; it does not follow the label. The correct punctuation after the label is the colon.

Common Pitfalls:
Omitting the colon or misplacing the semicolon causes syntax errors. Also, confusing component instantiation syntax with process or concurrent statement syntax can lead to formatting mistakes.

Final Answer:
colon