Static RAM (SRAM) data retention — does SRAM require periodic refresh every few milliseconds to avoid data loss, like DRAM does?

Introduction / Context:
Dynamic RAM (DRAM) and Static RAM (SRAM) store bits using different circuit principles. DRAM uses tiny capacitors that leak charge and therefore demand periodic refresh. SRAM uses cross-coupled latches that hold state indefinitely as long as the device is powered within specification, eliminating the need for refresh cycles.

Given Data / Assumptions:

• The statement asserts that SRAM must be refreshed every few milliseconds.
• We consider normal operating conditions with valid supply voltage and within the device’s temperature range.
• We are not considering power-down non-volatility.

Concept / Approach:
SRAM cells are typically 6-transistor latches. Once a 0 or 1 is written, transistor feedback maintains the state continuously while Vcc is present, independent of periodic rewriting. DRAM cells, by contrast, are 1-transistor/1-capacitor and require refresh because the capacitor’s charge decays. Therefore, refresh is a DRAM characteristic, not an SRAM requirement.

Step-by-Step Solution:

Verification / Alternative check:
Consult SRAM datasheets; there is no refresh timing parameter. DRAM datasheets include refresh intervals (e.g., 64 ms, 32 ms) and refresh command timing.

Why Other Options Are Wrong:

Common Pitfalls:
Assuming all volatile memories refresh; forgetting that SRAM loses data only on power removal or out-of-spec supply, not due to capacitor leakage.

Final Answer:
Incorrect — SRAM does not require refresh while powered