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- Question
Which is not a step used to define the scope of an HDL project?
Options- A. Are the inputs and outputs active HIGH or active LOW?
- B. A clear vision of how to make each block work
- C. What are the speed requirements?
- D. How many bits of data are needed?
- Correct Answer
- A clear vision of how to make each block work
- 1. In a digital clock application, the basic frequency must be divided down to:
Options- A. 1 Hz.
- B. 60 Hz.
- C. 100 Hz.
- D. 1000 Hz. Discuss
- 2. In the frequency counter, what is the function of the Schmitt trigger circuit?
Options- A. To reduce input noise
- B. To condition the input signal
- C. To convert non-square waveforms
- D. To provide a usable signal to the display unit Discuss
- 3. In the digital clock project, the purpose of the frequency prescaler is to:
Options- A. find the basic frequency.
- B. transform a 60 pps input to a 1 pps timing signal.
- C. prevent the clock from exceeding 12:59:59.
- D. allow the BCD display to have a value from 00?59. Discuss
- 4. Which is not a major block of an HDL frequency counter?
Options- A. Display register
- B. Decoder/display
- C. Timing and control unit
- D. Bit shifter Discuss
- 5. The accuracy of the frequency counter depends on the:
Options- A. system clock frequency.
- B. number of displayed digits.
- C. sampling rate.
- D. display update rate. Discuss
- 6. In the frequency counter, when is the new count stored in the display register?
Options- A. After disabling the counter
- B. When the count buffer is full
- C. After the sample interval is set
- D. When the timing and control block has put it there Discuss
- 7. In the digital clock project, what is the frequency of the MOD-6 counter in the minutes section?
Options- A. 1 pulse per minute
- B. 6 pulses per minute
- C. 10 pulses per minute
- D. 1 pulse per hour Discuss
- 8. In the frequency counter, if the clock generator produces a 100 kHz system clock signal, how many decade counters are required to measure 1 Hz?
Options- A. 6
- B. 5
- C. 4
- D. 3 Discuss
- 9. In the digital clock project, when does the PM indicator go high?
Options- A. Never
- B. Going from 11:59:59 to 12:00:00
- C. Going from 12:59:59 to 01:00:00
- D. On the falling edge of the clock after enable goes high Discuss
- 10. Which is not a step in strategic planning for HDL development?
Options- A. There must be a way to test each piece.
- B. Each block must fit together to make up the whole system.
- C. The names of each input and output must be known.
- D. The exact operation of each block must be thoroughly defined and understood. Discuss
Digital System Projects Using HDL problems
Search Results
Correct Answer: 1 Hz.
Correct Answer: To convert non-square waveforms
Correct Answer: transform a 60 pps input to a 1 pps timing signal.
Correct Answer: Bit shifter
Correct Answer: system clock frequency.
Correct Answer: After disabling the counter
Correct Answer: 1 pulse per hour
Correct Answer: 5
Correct Answer: Going from 11:59:59 to 12:00:00
Correct Answer: The names of each input and output must be known.
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