The toggle condition in a master-slave J-K flip-flop means that Q and will switc

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Question
The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.
Options
A. opposite, active clock edge
B. inverted, positive clock edge
C. quiescent, negative clock edge
D. reset, synchronous clock edge

Correct Answer

opposite, active clock edge

Flip-Flops problems

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3. A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?
Options
A. The power supply is probably noisy.
B. The switch contacts are bouncing.
C. The socket contacts on the register IC are corroded.
D. The register IC is intermittent and failure is imminent.

5. Which of the following is correct for a gated D flip-flop?
Options
A. The output toggles if one of the inputs is held HIGH.
B. Only one of the inputs can be HIGH at a time.
C. The output complement follows the input when enabled.
D. Q output follows the input D when the enable is HIGH.

7. What is the difference between a 7490 and a 7492?
Options
A. 7490 is a MOD-12, 7492 is a MOD-10
B. 7490 is a MOD-12, 7492 is a MOD-16
C. 7490 is a MOD-16, 7492 is a MOD-10
D. 7490 is a MOD-10, 7492 is a MOD-12

8. List the state of each output pin of a 7447 if RBI = 0, LT = 1, A₀ = 1, A₁ = 0, A₂ = 0, and A₃ = 1.
Options
A. RBO = 0, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0
B. RBO = 1, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0
C. RBO = 0, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0
D. RBO = 1, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0

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